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参数资料
| 型号： | ST10R272LT6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, TQFP-100 |
| 文件页数： | 43/77页 |
| 文件大小： | 707K |
| 代理商： | ST10R272LT6 |
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ST10R272L - ELECTRICAL CHARACTERISTICS
Prescaler operation
Set when pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the period of the input clock fXTAL.
The timings listed in the AC characteristics that refer to TCLs therefore can be calculated
using the period of fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset, the on-chip phase locked loop is
disabled and the CPU clock is driven from the internal oscillator with the input clock signal.
The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL.
The TCL timing below must be calculated using the minimum possible TCL which can be
calculated by the formula:
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so
the duration of 2TCL is always 1/fXTAL. Therefore, the minimum value TCLmin has to be used
only once for timings that require an odd number of TCLs (1,3,...). Timings that require an
even number of TCLs (2,4,...) may use the formula:
.
100
F
XTAL * 5
2 to 10 MHz
011
F
XTAL * 1
1 to 50 MHz
Direct drive 1)
010
F
XTAL * 1.5
6.66 to 33.33 MHz
001
F
XTAL / 2
2 to 100 MHz
CPU clock via 2:1 prescaler
000
F
XTAL * 2.5
4 to 20 MHz
1) The maximum depends on the duty cycle of the external clock signal. The maxi-
mum input frequency is 25 MHz when using an external crystal oscillator, but
higher frequencies can be applied with an external clock source.
P0.15-13 (P0H.7-5)
CPU frequency
fCPU = fXTAL * F
External clock
input range 10-
50MHz
Notes
Table 15 CPU clock generation mechanisms
TCL
min
1 f
XTAL
DC
min
×
DC
(
=
duty cycle
)
=
2TCL
1 f
XTAL
=
1
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