参数资料
型号: ST72651AR6T1E/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, ROHS COMPLIANT, TQFP-64
文件页数: 101/161页
文件大小: 2656K
代理商: ST72651AR6T1E/XXX
ST72651AR6
44/161
Doc ID 7215 Rev 4
POWER SAVING MODES (Cont’d)
8.3 HALT MODE
The HALT mode is the MCU lowest power con-
sumption mode. The HALT mode is entered by ex-
ecuting the HALT instruction. The internal oscilla-
tor is then turned off, causing all internal process-
ing to be stopped, including the operation of the
on-chip peripherals.
When entering HALT mode, the I[1:0] bits in the
Condition Code Register are cleared. Thus, any of
the external interrupts (ITi or USB end suspend
mode), are allowed and if an interrupt occurs, the
CPU clock becomes active.
The MCU can exit HALT mode on reception of ei-
ther an external interrupt on ITi, a plug/unplug in-
terrupt, an end suspend mode interrupt coming
from USB peripheral, an SPI interrupt or a reset.
The oscillator is then turned on and a stabilization
time is provided before releasing CPU operation.
The stabilization time is 512 CPU clock cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Related Documentation
AN980: ST7 Keypad Decoding Techniques, Im-
plementing Wake-Up on Keystroke
AN1014: How to Minimize the ST7 Power Con-
sumption
AN1605: Using an active RC to wakeup the
ST7LITE0 from power saving mode
Figure 30. HALT Mode Flow Chart
N
EXTERNAL
INTERRUPT*
RESET
HALT INSTRUCTION
FETCH RESET VECTOR
OR SERVICE INTERRUPT
DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I1:0] BITS
ON
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I1:0] BITS
OFF
CLEARED
OFF
Y
Note: Before servicing an interrupt, the CC
register is pushed on the stack. TheI1:0] bits are
set during the interrupt routine and cleared
when the CC register is popped.
(Refer to Figure 19 and
1
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