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参数资料
| 型号： | ST72651AR6T1E/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, ROHS COMPLIANT, TQFP-64 |
| 文件页数： | 127/161页 |
| 文件大小： | 2656K |
| 代理商： | ST72651AR6T1E/XXX |
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ST72651AR6
68/161
Doc ID 7215 Rev 4
USB INTERFACE (Cont’d)
Bit 4 = ERR Error.
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit stuffing, nonstandard
framing or buffer overrun error detected
Note: Refer to the ERR[2:0] bits in the USBSR
register to determine the error type.
Bit 3 = SUSP Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB.
The suspend request check is active immediately
after each USB reset event and is disabled by
hardware when suspend mode is forced (FSUSP
bit in the CTLR register) until the end of resume
sequence.
Bit 2 = ESUSP End Suspend mode.
This bit is set by hardware when, during suspend
mode, activity is detected that wakes the USB in-
terface up from suspend mode.
This interrupt is serviced by a specific vector, in or-
der to wake up the ST7 from HALT mode.
0: No End Suspend detected
1: End Suspend detected
Bit 1 = RESET USB reset.
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0R, EP1RXR, EP1TXR
and EP2RXR, EP2TXR registers are reset by a
USB reset.
Bit 0 = SOF Start of frame.
This bit is set by hardware when a SOF token is re-
ceived on the USB.
0: No SOF received
1: SOF received
Note: To avoid spurious clearing of some bits, it is
recommended to clear them using a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND, XOR.
INTERRUPT MASK REGISTER (IMR)
Read/Write
Reset Value: 0000 0000 (00h)
These bits are mask bits for all the interrupt condi-
tion bits included in the ISTR register. Whenever
one of the IMR bits is set, if the corresponding
ISTR bit is set, and the I- bit in the CC register is
cleared, an interrupt request is generated. For an
explanation of each bit, please refer to the descrip-
tion of the ISTR register.
CONTROL REGISTER (CTLR)
Read/Write
Reset value: 0000 0110 (06h)
Bit 7 = RSM Resume Detected
This bit shows when a resume sequence has start-
ed on the USB port, requesting the USB interface
to wake-up from suspend state. It can be used to
determine the cause of an ESUSP event.
0: No resume sequence detected on USB
1: Resume sequence detected on USB
Bit 6 = USB_RST USB Reset detected.
This bit shows that a reset sequence has started
on the USB. It can be used to determine the cause
of an ESUSP event (Reset sequence).
0: No reset sequence detected on USB
1: Reset sequence detected on USB
Bits 5:4 Reserved, forced by hardware to 0.
Bit 3 = RESUME Resume.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Resume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after the appropriate
delay.
70
CTRM
0
SOVR
M
ERRM
SUSP
M
ESUSP
M
RESET
M
SOFM
70
RSM
USB_
RST
00
RESU
ME
PDWN
FSUSP
FRES
1
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