参数资料
型号: ST72F324K2B1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封装: 0.400 INCH, SHRINK, PLASTIC, DIP-32
文件页数: 75/156页
文件大小: 1012K
代理商: ST72F324K2B1
ST72324J/K
25/156
RESET SEQUENCE MANAGER (Cont’d)
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 14), the
signal on the RESET pin will be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 14).
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
6.3.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
s
Power-On RESET
s
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 14.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 14. RESET Sequences
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
tw(RSTL)out
RUN
th(RSTL)in
ACTIVE
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
tw(RSTL)out
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
DELAY
相关PDF资料
PDF描述
ST72F324K6B1 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
ST72F324J4B1 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP42
ST72F324J6B3 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP42
ST72F324K2B3 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
ST72F324K4B5 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
相关代理商/技术参数
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