参数资料
型号: ST92163N4G0
厂商: 意法半导体
英文描述: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
中文描述: 16位产品全速USB微控制器16端点,20,000光盘和2K的RAM,I2C和脊髓损伤的复合设备,
文件页数: 187/224页
文件大小: 1372K
代理商: ST92163N4G0
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ST92163 - I2C BUS INTERFACE
I
2
C INTERFACE
(Cont’d)
Bit 0 =
ITE
Interrupt Enable.
The ITE bit enables the generation of interrupts.
This bit is set and cleared by softwareand cleared
by hardware when the interface is disabled
(I2CCR.PE=0).
0: Interrupts disabled (reset value)
1: Interrupts enabledafter anyof thefollowing con-
ditions:
– Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after bytetransmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
– Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
– Address byte successfully transmitted in Mas-
ter mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX = 1)
SCL is held low when the ADDTX flag of the
I2CSR2 register or the ADD10, SB, BTF or ADSL
flags of I2CSR1 register are set (See Figure 84) or
when the DMA is not complete.
The transfer is suspended in all cases except
when the BTF bit is set and the DMA is enabled. In
this case the event routine must suspend the DMA
transfer if it is required.
I
2
C STATUS REGISTER 1 (I2CSR1)
R241 - Read Only
Register Page: 20
Reset Value: 0000 0000 (00h)
Note:
Some bitsof this register are reset by a read
operation of the register. Care must be takenwhen
using instructions that work on single bit. Some of
them perform a read of all the bits of the register
before modifying or testing the wanted bit. So oth-
er bits of the register could be affected by the op-
eration.
In thesame way, thetest/compare operations per-
form a read operation.
Moreover, if some interrupt events occur while the
register is read, the corresponding flags are set,
and correctly read, but if the read operation resets
the flags, no interrupt request occurs.
Bit 7 =
EVF
Event Flag.
This bit is set by hardware as soon as an event (
listed below or described in Figure 84) occurs. It is
cleared by software when all event conditions that
set the flag are cleared. It is also cleared by hard-
ware
when
the
interface
(I2CCR.PE=0).
0: No event
1: One of the following events has occurred:
– Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
– Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
– Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
– No acknowledge received after byte transmis-
sion
(I2CSR2.AF and I2CSR1.EVF flags = 1)
– Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
– Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
– Bus error, Start or Stop condition detected
during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
– Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
is
disabled
7
0
EVF
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
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