参数资料
型号: ST92163N4G0
厂商: 意法半导体
英文描述: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
中文描述: 16位产品全速USB微控制器16端点,20,000光盘和2K的RAM,I2C和脊髓损伤的复合设备,
文件页数: 49/224页
文件大小: 1372K
代理商: ST92163N4G0
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ST92163 - INTERRUPTS
with the highest position in the chain, as shown in
Table 10.
Table 10. Daisy Chain Priority
3.4.4 Dynamic Priority Level Modification
The main program and routines can bespecifically
prioritized. Since the CPL is represented by 3 bits
in a read/write register, it is possible to modify dy-
namically the current priority value during program
execution. This means that a critical section can
have a higher priority with respect to other inter-
rupt requests. Furthermore it is possible to priori-
tize even the Main Program execution by modify-
ing the CPL during its execution. See Figure 21
Figure 21. Example of Dynamic priority
level modification in NestedMode
INTERRUPT 6 HAS PRIORITY LEVEL 6
3.5 ARBITRATION MODES
The ST9 provides two interrupt arbitration modes:
Concurrent mode and Nested mode. Concurrent
mode is the standard interrupt arbitration mode.
Nested mode improves the effective interrupt re-
sponse time when service routine nesting is re-
quired, depending on the request priority levels.
The IAM control bit in the CICR Register selects
Concurrent Arbitration mode or Nested Arbitration
Mode.
3.5.1 Concurrent Mode
This mode is selected when the IAM bit is cleared
(reset condition). The arbitration phase, performed
during every instruction, selects the request with
the highest priority level. The CPL value is not
modified in this mode.
Start of Interrupt Routine
The interrupt cycle performs the following steps:
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bitvector stored in
the Vector Table, pointed to by the IVR.
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwiseISR isused inplaceof CSRuntil
iret
instruction.
End of Interrupt Routine
The Interrupt Service Routine must be ended with
the
iret
instruction. The
iret
instruction exe-
cutes the following operations:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– If ENCSR is reset, CSR is used instead of ISR.
Normal program execution thus resumesat the in-
terrupted instruction. All pending interrupts remain
pending until the next
ei
instruction (even if it is
executed during the interrupt service routine).
Note
: In Concurrent mode, the sourcepriority level
is only useful during thearbitration phase, where it
is compared with all other priority levels and with
the CPL. No trace is kept of its value during the
ISR. If other requests are issued during the inter-
rupt service routine, once the global CICR.IEN is
re-enabled, they will be acknowledged regardless
of the interrupt service routine’s priority. This may
cause undesirable interrupt response sequences.
Highest Position
Lowest Position
INTA0
INTA1
INTB0
INTB1
INTC0
INTC1
INTD0
INTD1
USB
MFT
SCI
I2C
INT0/WDT
INT1/ADC
INT2
INT3
INT4/
INT5
INT6/RCCU
INT7/WKUP
6
5
4
7
Priority Level
MAIN
CPL is set to 5
CPL=7
MAIN
INT 6
CPL=6
INT6
ei
CPL is set to 7
by MAIN program
CPL6 > CPL5:
INT6 pending
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