参数资料
型号: ST92163N4G0
厂商: 意法半导体
英文描述: 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
中文描述: 16位产品全速USB微控制器16端点,20,000光盘和2K的RAM,I2C和脊髓损伤的复合设备,
文件页数: 30/224页
文件大小: 1372K
代理商: ST92163N4G0
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ST92163 - DEVICE ARCHITECTURE
2.3 SYSTEM REGISTERS
The System registers are listed in Table 2 System
Registers (Group E). They are used to perform all
the importantsystem settings. Their purpose is de-
scribed in the following pages. Referto the chapter
dealing with I/O for a description of the PORT[5:0]
Data registers.
Table 9. System Registers (Group E)
2.3.1 Central Interrupt Control Register
Please referto the ”INTERRUPT” chapter for a de-
tailed description of the ST9 interrupt philosophy.
CENTRAL INTERRUPT CONTROL REGISTER
(CICR)
R230 - Read/Write
Register Group: E (System)
Reset Value: 1000 0111 (87h)
Bit 7 =
GCEN
: Global Counter Enable
This bit is the Global Counter Enable of the Multi-
function Timers. The GCEN bit is ANDed with the
CE bit in theTCR Register (only in devices featur-
ing theMFT Multifunction Timer) in order to enable
the Timers when both bits are set.This bit is set af-
ter the Reset cycle.
Note:
If an MFT is not included in the ST9 device,
then this bit has no effect.
Bit 6 =
TLIP
: Top Level Interrupt Pending.
This bit is set by hardware when a Top Level Inter-
rupt Request is recognized. This bit can also be
set by software to simulate a Top Level Interrupt
Request.
0: No Top Level Interrupt pending
1: Top Level Interrupt pending
Bit 5 =
TLI
: Top Level Interrupt bit
0: Top Level Interrupt is acknowledged depending
on the TLNM bit in the NICR Register.
1: Top Level Interrupt is acknowledged depending
on theIEN and TLNM bitsin theNICR Register
(described in the Interrupt chapter).
Bit 4 =
IEN
: Interrupt Enable .
This bit is cleared by interrupt acknowledgement,
and set by interrupt return (
iret
). IEN is modified
implicitly by
iret
,
ei
and
di
instructions or by an
interrupt acknowledge cycle. It can also be explic-
itly written by the user, but only when no interrupt
is pending. Therefore, the user should execute a
di
instruction (or guarantee by other means that
no interrupt request can arrive) before any write
operation to the CICR register.
0: Disableall interrupts exceptTopLevel Interrupt.
1: Enable Interrupts
Bit 3 =
IAM
: Interrupt Arbitration Mode
This bit is set and clearedby software to select the
arbitration mode.
0: Concurrent Mode
1: Nested Mode.
Bit 2:0 =
CPL[2:0]
: Current Priority Level
These three bits record the priority level of the rou-
tine currently running (i.e. the Current Priority Lev-
el, CPL). The highest priority level is represented
by 000, and the lowest by 111. The CPL bits can
be set by hardware or software and provide the
reference according to which subsequent inter-
rupts are eitherleft pending or are allowed to inter-
rupt the current interrupt service routine. When the
current interrupt is replacedby one of a higher pri-
ority, the current priority value is automatically
stored until required in the NICR register.
R239 (EFh)
R238 (EEh)
R237 (EDh)
R236 (ECh)
R235 (EBh)
R234 (EAh)
R233 (E9h)
R232 (E8h)
R231 (E7h)
R230 (E6h)
R229 (E5h)
R228 (E4h)
R227 (E3h)
R226 (E2h)
R225 (E1h)
R224 (E0h)
SSPLR
SSPHR
USPLR
USPHR
MODE REGISTER
PAGE POINTER REGISTER
REGISTER POINTER 1
REGISTER POINTER 0
FLAG REGISTER
CENTRAL INT. CNTL REG
PORT5 DATA REG.
PORT4 DATA REG.
PORT3 DATA REG.
PORT2 DATA REG.
PORT1 DATA REG.
PORT0 DATA REG.
7
0
GCEN
TLIP
TLI
IEN
IAM
CPL2 CPL1 CPL0
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ST92163N4G0V 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
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ST92163N4G0E 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT
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