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参数资料
| 型号： | ST92R195C9 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | PLASTIC, QFP-80 |
| 文件页数： | 144/208页 |
| 文件大小： | 2312K |
| 代理商： | ST92R195C9 |
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ST92R195C - INTERRUPTS
3.2.2
Segment
Paging
During
Interrupt
Routines
The ENCSR bit in the EMR2 register can be used
to select between original ST9 backward compati-
bility mode and ST9+ interrupt management
mode.
ST9 backward compatibility mode (ENCSR = 0)
If ENCSR is reset, the CPU works in original ST9
compatibility mode. For the duration of the inter-
rupt service routine, ISR is used instead of CSR,
and the interrupt stack frame is identical to that of
the original ST9: only the PC and Flags are
pushed.
This avoids saving the CSR on the stack in the
event of an interrupt, thus ensuring a faster inter-
rupt response time.
It is not possible for an interrupt service routine to
perform inter-segment calls or jumps: these in-
structions would update the CSR, which, in this
case, is not used (ISR is used instead). The code
segment size for all interrupt service routines is
thus limited to 64K bytes.
ST9+ mode (ENCSR = 1)
If ENCSR is set, ISR is only used to point to the in-
terrupt vector table and to initialize the CSR at the
beginning of the interrupt service routine: the old
CSR is pushed onto the stack together with the PC
and flags, and CSR is then loaded with the con-
tents of ISR.
In this case, iret will also restore CSR from the
stack. This approach allows interrupt service rou-
tines to access the entire 4 Mbytes of address
space. The drawback is that the interrupt response
time is slightly increased, because of the need to
also save CSR on the stack.
Full compatibility with the original ST9 is lost in this
case, because the interrupt stack frame is differ-
ent.
3.3 INTERRUPT PRIORITY LEVELS
The ST9 supports a fully programmable interrupt
priority structure. Nine priority levels are available
to define the channel priority relationships:
– The on-chip peripheral channels and the eight
external interrupt sources can be programmed
within eight priority levels. Each channel has a 3-
bit field, PRL (Priority Level), that defines its pri-
ority level in the range from 0 (highest priority) to
7 (lowest priority).
– The 9th level (Top Level Priority) is reserved for
the Timer/Watchdog or the External Pseudo
Non-Maskable Interrupt. An Interrupt service
routine at this level cannot be interrupted in any
arbitration mode. Its mask can be both maskable
(TLI) or non-maskable (TLNM).
3.4 PRIORITY LEVEL ARBITRATION
The 3 bits of CPL (Current Priority Level) in the
Central Interrupt Control Register contain the pri-
ority of the currently running program (CPU priori-
ty). CPL is set to 7 (lowest priority) upon reset and
can be modified during program execution either
by software or automatically by hardware accord-
ing to the selected Arbitration Mode.
During every instruction, an arbitration phase
takes place, during which, for every channel capa-
ble of generating an Interrupt, each priority level is
compared to all the other requests (interrupts or
DMA).
If the highest priority request is an interrupt, its
PRL value must be strictly lower (that is, higher pri-
ority) than the CPL value stored in the CICR regis-
ter (R230) in order to be acknowledged. The Top
Level Interrupt overrides every other priority.
3.4.1 Priority level 7 (Lowest)
Interrupt requests at PRL level 7 cannot be ac-
knowledged, as this PRL value (the lowest possi-
ble priority) cannot be strictly lower than the CPL
value. This can be of use in a fully polled interrupt
environment.
3.4.2 Maximum depth of nesting
No more than 8 routines can be nested. If an inter-
rupt routine at level N is being serviced, no other
Interrupts located at level N can interrupt it. This
guarantees a maximum number of 8 nested levels
including the Top Level Interrupt request.
3.4.3 Simultaneous Interrupts
If two or more requests occur at the same time and
at the same priority level, an on-chip daisy chain,
specific to every ST9 version, selects the channel
ENCSR Bit
0
1
Mode
ST9 Compatible
ST9+
Pushed/Popped
Registers
PC, FLAGR
PC, FLAGR,
CSR
Max. Code Size
for interrupt
service routine
64KB
Within 1 segment
No limit
Across segments
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相关代理商/技术参数 |
参数描述 |
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| ST92T141K4B6 | 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST92T141K4M6 | 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST92T163R4T1 | 功能描述:8位微控制器 -MCU OTP EPROM 20K USB/I2 RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST92T196/JAP | 制造商:STMicroelectronics 功能描述: |
| ST92T96N9B1/AIN | 制造商:STMicroelectronics 功能描述: |
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