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ST92R195C - RESET AND CLOCK CONTROL UNIT (RCCU)
OSCILLATOR CHARACTERISTICS (Cont’d)
The following table is relative to the fundamental
quartz crystal only; assuming:
– Rs: parasitic series resistance of the quartz crys-
tal (upper limit)
– C0: parasitic capacitance of the crystal (upper
limit,
≤ 7pF)
– C1,C2: maximum total capacitance on pins OS-
CIN/OSCOUT (value including external capaci-
tance tied to the pin plus the parasitic
capacitance of the board and device).
Table 9. Crystal Specification (C0
≤ 7pF)
Legend:
Rs: Parasitic Series Resistance of the quartz crystal (up-
per limit) C0: Parasitic capacitance of the quartz crystal
(upper limit, < 7pF)
C1, C2: Maximum Total Capacitance on pins OSCIN and
OSCOUT (the value includes the external capacitance
tied to the pin plus the parasitic capacitance of the board
and of the device)
gm: Transconductance of the oscillator
Note.The tables are relative to the fundamental quartz
crystal only (not ceramic resonator).
5.4 CLOCK CONTROL REGISTERS
MODE REGISTER (MODER)
R235 - Read/Write
Register Group: E (System)
Reset Value: 1110 0000 (E0h)
Bit 7:6 = Bits described in Device Architecture
chapter.
Bit 5 = DIV2:
OSCIN Divided by 2.
This bit controls the divide by 2 circuit which oper-
ates on the OSCIN Clock.
0: No division of OSCIN Clock
1: OSCIN clock is internally divided by 2
Bit 4:2 = PRS[2:0]:
Clock Prescaling.
These bits define the prescaler value used to
prescale CPUCLK from INTCLK. When they are
reset, the CPUCLK is not prescaled, and is equal
to INTCLK; in all other cases, the internal clock is
prescaled by the value of these three bits plus one.
Bit 1:0 = Bits described in Device Architecture
chapter.
WAIT CONTROL REGISTER (WCR)
R252 - Read/Write
Register Page: 0
Reset Value: 0111 1111 (7Fh)
Bit 7 = Reserved, read as “0”.
Bit 6 = WDGEN: refer to Timer/Watchdog chapter.
WARNING. Resetting this bit to zero has the effect
of setting the Timer/Watchdog to the Watchdog
mode. Unless this is desired, this must be set to
“1”.
Bit 5:3 = WDM[2:0]:
Data Memory Wait Cycles.
These bits contain the number of INTCLK cycles
to be added automatically to external Data memo-
ry accesses. WDM = 0 gives no additional wait cy-
cles. WDM = 7 provides the maximum 7 INTCLK
cycles (reset condition).
Bit 2:0 = WPM[2:0]:
Program Memory Wait Cy-
cles.
These bits contain the number of INTCLK cycles
to be added automatically to external Program
memory accesses. WPM = 0 gives no additional
wait cycles, WPM = 7 provides the maximum 7
INTCLK cycles (reset condition).
Note: The number of clock cycles added refers to
INTCLK and NOT to CPUCLK.
WARNING. The reset value of the Wait Control
Register gives the maximum number of Wait cy-
cles for external memory. To get optimum per-
formance from the ST9 when used in single-chip
mode (no external memory) the user should write
the WDM2,1,0 and WPM2,1,0 bits to “0”.
Frequency
C1 =C2=39 pF
Rs Max
865
4260
70
11
DIV2
PRS2
PRS1
PRS0
00
70
0
WDGEN WDM2 WDM1
WDM0
WPM2 WPM1 WPM0