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参数资料
| 型号： | STEL-1177/CF |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CPGA84 |
| 封装： | CERAMIC, PGA-84 |
| 文件页数： | 14/17页 |
| 文件大小： | 224K |
| 代理商： | STEL-1177/CF |
STEL-1177
6
DATA7
through
DATA0
The 8-bit DATA7-0 bus is used to program the two 32-
bit
-Phase Registers and the two 12-bit Phase
Modulation Registers. DATA0 is the least significant
bit of the bus. The data programmed into the
-Phase
registers in this way determines the carrier frequency
of the NCO.
ADDR3
through
ADDR0
The four address lines ADDR3-0 control the use of the
DATA7-0 bus for writing frequency data to the -
Phase Buffer Registers, and phase data to the Phase
Buffer Registers, as shown in the table:
ADDR3 ADDR1 ADDR0 Register Field
00
0
-Phase Bits 0 (LSB)–7
00
1
-Phase Bits 8–15
01
0
-Phase Bits 16–23
01
1
-Phase Bits 24–31
1
0
Sine Bits 0(LSB)–3*
1
0
1
Sine Bits 4-11*
1
0
Cosine Bits 0(LSB)–3*
1
Cosine Bits 4-11*
ADDR3 ADDR2
Register Selected
00
-Phase Buffer Register 'A'
01
-Phase Buffer Register 'B'
1
X
Phase Buffer Registers
* Note: The Phase Buffer Registers are 12-bit registers.
When the least significant bytes of these registers are
selected (ADDR3-0 =1XX0), DATA7-4 is written into
Bits 3–0 of the registers. In all cases, it is not necessary
to reload unchanged bytes, and the byte loading
sequence may be random.
WRSTB
The Write Strobe input is used to latch the data on the
DATA7-0 bus into the device. On the rising edge of the
WRSTB
input, the information on the 8-bit data bus is
transferred to the buffer register selected by the
ADDR3-0 bus.
FRSEL
The Frequency Register Select line is used to control
the mux which selects the
-Phase Buffer Register in
use. When this signal is high
-Phase Buffer Register
'A' is selected as the source for the
-Phase ALU, and
the frequency corresponding to the data stored in this
register will be generated by the NCO after the next
falling edge on the FRLD input. When this line is low,
-Phase Buffer Register 'B' is selected as the source.
PHASE
ACCUMULATOR
BLOCK
This block forms the core of the NCO function. It is a
high-speed, pipelined, 32-bit parallel accumulator,
generating a new sum in every clock cycle. A carry
input (the CIN input) allows the resolution of the
accumulator to be expanded by means of an auxiliary
NCO or phase accumulator. The overflow signal is
discarded, since the required output is the
modulo(232) sum only. This represents the modulo(2
π)
phase angle.
PHASE
ALU
BLOCKS
The two Phase ALUs perform the addition of the sine
and cosine PM data to the Phase Accumulator output
in the sine and cosine channels, respectively. The PM
data words are both 12 bits wide, and these are added
to the 13 most significant bits from the Phase
Accumulator to form the modulated phase used to
address the lookup tables.
SINE
AND
COSINE
LOOKUP
TABLE
BLOCKS
These blocks are the sine and cosine memories. The 13
bits from the Phase ALUs are used to address these
memories to generate the 12-bit SINE11-0 and COS11-0
outputs. The Cosine LUT can be disabled when not in
use, to conserve power, by means of the COSEN
input.
INPUT
SIGNALS
RESET
The RESET input is asynchronous and active low, and
clears all the registers in the device. When RESET goes
low, all registers are cleared within 20 nsecs, and
normal operation will resume after this signal returns
high. The data on the SINE11-0 and COS11-0 buses will
then be invalid for 7 clock cycles, and thereafter will
remain at the value corresponding to zero phase until
new frequency or modulation (either frequency or
phase) data is loaded with the FRLD, FMLD, or
PHLD
inputs after the RESET returns high.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be nominally a square
wave at a maximum frequency of 60 MHz. A non-
repetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 5 nanoseconds.
CSEL
The Chip Select input is used to control the writing of
data into the chip. It is active low. When this input is
high all data writing via the DATA7-0 bus is inhibited.
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