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参数资料
| 型号： | STEL-1177/CF |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CPGA84 |
| 封装： | CERAMIC, PGA-84 |
| 文件页数： | 15/17页 |
| 文件大小： | 224K |
| 代理商： | STEL-1177/CF |
7
STEL-1177
FMADDR1
through
FMADDR0
The two inputs FMADDR1-0 set the deviation of the
frequency modulation by controlling the significance
of the FM data in relation to the carrier frequency data.
The FM data word will be multiplied by 20, 24, 28, or
212 according to the state of FMADDR1-0, and the
consequent resolution and maximum values of the
deviation are shown in the table below. The values
shown are for a clock frequency of 60 MHz.
FM-
Mult. factor Maximum
Resol-
ADDR1 ADDR0 of FM data
deviation
ution
00
20
± 915 Hz
14 mHz
01
24
± 14.6 KHz 0.22 Hz
10
28
± 234 KHz 3.6 Hz
11
212
± 3.75 MHz 57 Hz
FMLD
The FM Load input controls the writing of the
frequency modulation data on the FMOD15-0 bus and
the FMSUB input into the device. When RATE1-0= 00
the data at the output of the Frequency Modulation
Control Block must be valid during the clock cycle
following the falling edge of FMLD. The data is then
transferred during the subsequent cycle. When
RATE1-0= 01, 10 or 11 are selected the FM data will be
loaded automatically without the use of the FMLD
input. Note that FMLD must be held low during
automatic operation, otherwise the loading will be
inhibited.
SIMLD
The Simultaneous Load input allows the carrier
frequency data from the Mux Block and the FM data
to be updated simultaneously. When SIMLD is low,
only the FM data will be updated after a falling edge
on FMLD. When this input is high, both the FM data
and carrier frequency data will be updated
simultaneously. When SIMLD is low at least four
clock cycles are required between falling edges of
FMLD
and FRLD to ensure glitch-free changes in the
outputs.
RATE 1-0
The RATE1-0 signals control the rate at which the FM
data on the FMOD15-0 bus is added to or subtracted
from the carrier frequency, as shown in the table
below:
RATE1 RATE0
Modulation Update Rate
0
Manual, with FMLD signal
0
1
Every 4th clock cycle
1
0
Every 8th clock cycle
1
Every 16th clock cycle
FRLD
The Frequency Load input is used to control the
transfer of the data from the
-Phase Buffer Registers
to the
-Phase ALU. The data at the output of the Mux
Block must be valid during the clock cycle following
the falling edge of FRLD. The data is then transferred
during the subsequent cycle. The frequency of the
NCO output will change 19 clock cycles after the
FRLD
command due to pipelining delays.
PHSEL
The Phase Source Select input selects the sources of
data for the Phase ALUs. When it is high the sources
are the Sine and Cosine Phase Buffer Registers. They
are loaded from the DATA7-0 bus by setting address
line ADDR3 high, as shown in the tables. When
PHSEL
is low, the sources for the phase modulation
data are the DATA7-0 and ADDR3-0 inputs, and the
data will be loaded independently of the states of
WRSTB
and CSEL. The data on these 12 lines is
presented directly as a parallel 12-bit word to both
Phase ALUs, allowing high-speed phase modulation.
The 12-bit value is latched into the Phase ALUs by
means of the PHLD input. The data on the ADDR3-0
lines is mapped onto Phase Bits 3 to 0 and the data on
the DATA7-0 lines are mapped onto Phase Bits 11 to 4
in this case. When using the parallel phase load mode
CSEL
and/or WRSTB should remain high to ensure
that the phase data is not written into the phase and
frequency buffer registers of the STEL-1177.
PHLD
The Phase Load input is used to control the latching of
the Phase Modulation data into the Phase ALUs. The
12-bit data at the output of the Phase Modulation
Control Block must be valid during the clock cycle
following the falling edge of PHLD. The data is then
transferred during the subsequent cycle. The 12-bit
phase data is added to the 12 most significant bits of
the accumulator output, so that the MSB of the phase
data represents a 180
° phase change. The source of this
data will be determined by the state of PHSEL. The
phase of the NCO output will change 12 clock cycles
after the PHLD command, due to pipelining delays.
FMOD15
through
FMOD0
The Frequency Modulation bus is a 16-bit bus on
which the FM data is loaded into the STEL-1177. The
data should be a 16-bit unsigned number.
FMSUB
The FM Subtract input controls the Add/Subtract
operation of the
-Phase ALU. When it is high the FM
data on the FMOD15-0 bus will be subtracted from the
carrier frequency, and when it is low the FM data will
be added to the carrier frequency. In this way the FM
data can be treated as a 17-bit signed-magnitude
number, where the FMSUB signal is the sign bit.
FMSUB
is latched at the same time as FMOD15-0.
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