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参数资料
| 型号： | STEL-1177/CF |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CPGA84 |
| 封装： | CERAMIC, PGA-84 |
| 文件页数： | 6/17页 |
| 文件大小： | 224K |
| 代理商： | STEL-1177/CF |
STEL-1177
14
It is possible to update the frequency at up to 25% of
the clock frequency using only one buffer register. The
timing for this procedure is shown in the diagram
below, and must be adhered to rigorously in order to
assure adequate setup and hold times. The most
critical factor is the setup time (tSU) for the WRSTB
relative to the clock (rising edge to rising edge). This
must be 8 nsec. for correct operation. Since this may
be slightly more than half the clock period at high
speeds some advantage can be gained by generating
the clock by inverting the WRSTB signal, rather than
the other way around. This makes the propagation
delay of the inverter used work for the timing
requirements instead of against them, since the hold
time requirement from the previous rising edge of the
clock (tHD) is 2 nsec.
HIGH-SPEED
FREQUENCY
CHANGE
The frequency of the STEL-1177 NCO can be changed
as rapidly as 25% of the clock frequency. This is done
by synchronizing the writing to the two
-Phase
Buffer Registers, and updating both every eight clock
cycles. The timing for this procedure is shown below.
Each
-Phase Buffer Register is loaded while the
contents of the other are being transferred into the
ALU Buffer Register. The sequence for a load cycle
begins on the rising edge of the clock following a
falling edge of FRLD (or a falling edge of FMLD if
SIMLD
is high). In the diagram below,
-Phase Buffer
Register A is being loaded in clock cycles 1 through 4,
while the contents of
-Phase Buffer Register B are
being transferred, because FRSEL was low during the
falling edge of FRLD. The reverse process happens
during clock cycles 5 through 8, and the process then
repeats starting in clock cycle 9. The FRLD signal can
be used to clock a bistable latch to generate the FRSEL
signal. The maximum update rate is 25%.
FRLD
CLOCK
WRSTB
ADDR
FRSEL
0100
0101
0110
0011
0000
0001
0010
123456789
0111
0000
0111
FRSEL=1
FRLD
CLOCK
WRSTB
ADDR 3-0
0011
0001
0010
123456789
0000
0011
0000
0001
0010
0001
tSU
tHD
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