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参数资料
| 型号： | STEL-1177/CF |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CPGA84 |
| 封装： | CERAMIC, PGA-84 |
| 文件页数： | 16/17页 |
| 文件大小： | 224K |
| 代理商： | STEL-1177/CF |
STEL-1177
8
CIN
The Carry Input is an arithmetic carry to the least
significant bit of the Accumulator. Normal operation
of the NCO requires that CIN be set at a logic 0. When
CIN
is set at a logic 1 the effective value of the
-Phase
register is increased by one. This allows the resolution
of the accumulator to be expanded for higher
frequency resolution.
ROUND
The ROUND input controls the precision of the
SINE11-0 and COS11-0 outputs. When the ROUND
input is set high, the sine and cosine signals appearing
on the SINE11-0 and COS11-0 buses are accurate to 12
bits. In some instances it may be desirable to use only
the 8 MSBs of these outputs. In such circumstances
the outputs appearing on the SINE11-0 and COS11-0
buses can be rounded to present a more accurate 8-bit
representation of the signal by setting the ROUND
input low.
COSEN
The Cosine Enable input controls the power supply to
the Cosine Lookup Table. When it is low the cosine
lookup table in the STEL-1177 is disabled, and only
the SINE11-0 outputs will be valid. This reduces the
power consumption of the device by approximately
30%.
OUTPUT
SIGNALS
SINE 11-0
The signal appearing on the SINE11-0 outputs is
derived from the 13 most significant bits of the Phase
Accumulator. The 12-bit sine function is presented in
offset binary format. When the phase accumulator is
zero, e.g., after a reset, the decimal value of the output
is 2049 (801H). When the phase modulation is zero the
value of the output for a given phase value follows the
relationship:
SINE11-0=2047 x sin (360 x (phase+0.5)/8192)°+2048
The result is accurate to within 1 LSB. However, when
ROUND
is set low, the value appearing on the
SINE11-0 outputs will be rounded and will follow the
relationship:
SINE11-4=127 x sin (360 x (phase+0.5)/8192)°+128
The data appearing on the SINE3-0 outputs will not be
meaningful under these circumstances.
COS 11-0
The signal appearing on the COS11-0 outputs is
derived from the 13 most significant bits of the Phase
Accumulator. The 12-bit cosine function is presented
in offset binary format. When the phase accumulator
is zero, e.g., after a reset, the decimal value of the
output is 4095 (FFFH). When the phase modulation is
zero the value of the output for a given phase value
follows the relationship:
COS11-0=2047 x cos (360 x (phase+0.5)/8192)°+2048
The result is accurate to within 1 LSB. However, when
ROUND
is set low, the value appearing on the COS11-
0 outputs will be rounded and will follow the
relationship:
COS11-4=127 x cos (360 x (phase+0.5)/8192)°+128
The data appearing on the COS3-0 outputs will not be
meaningful under these circumstances.
SYNC
The Sync output indicates the instant in time when
the frequency, FM, or PM change made at the inputs
affects the SINE11-0 and COS11-0 output signals. The
normally high SYNC output goes low for one clock
cycle 19 clock cycles after an FRLD or FMLD
command, and 12 clock cycles after a PHLD
command, to indicate the end of the pipeline delay
and the start of the new steady state condition.
FMSYNC
The FM Sync output indicates the instant in time when
the FM data on the FMOD bus is written into the
device. The FMSYNC output is normally high and
goes low for one clock cycle at a frequency depending
on the state of the RATE1-0 inputs. In the automatic
modulation modes (RATE1-0 ≠ 00) the data on the
FMOD15-0 bus will be written into the FM Buffer
Register on the rising edge of the clock following the
falling edge of FMSYNC. This signal can be used to
synchronize the updating of the FM data externally.
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