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参数资料
| 型号： | STEL-1177/CF |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CPGA84 |
| 封装： | CERAMIC, PGA-84 |
| 文件页数： | 4/17页 |
| 文件大小： | 224K |
| 代理商： | STEL-1177/CF |
STEL-1177
12
2.
PHSEL=1.
BUS
LOADING.
NCO
PHASE
CHANGE
SEQUENCE
WRSTB
ADDR 3-0
DATA 7-0
PHLD
PSYNC
CLOCK
CSEL
DON'T CARE
12 CLOCK
EDGES
OLD PHASE
NEW PHASE
DON'T CARE
tSU
tHD
tWR
tSU
tW
SINE 11-0
COS 11-0
ELECTRICAL
CHARACTERISTICS
A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ± 5%, VSS=0 V, Ta= 0° to 70° C, Chimerical
VDD= 5.0 V ± 10%, VSS=0 V, Ta=–55° to 125° C, Military)
Commercial
Military
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Units
Conditions
tCH
CLOCK
high
5
nsec.
fCLK = 60 MHz
8
nsec.
fCLK = 40 MHz
tCH
CLOCK
low
5
nsec.
fCLK = 60 MHz
8
nsec.
fCLK = 40 MHz
tW
WRSTB
, FRLD, PHLD
5
8
nsec.
or FMLD pulse width
tCD
CLOCK
to output delay
7
12
3
20
nsec.
Load = 15 pF
(All outputs)
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