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参数资料
型号： STM32F205RET6TR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP64
封装： 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件页数： 14/163页
文件大小： 2275K
代理商： STM32F205RET6TR
Electrical characteristics
STM32F205xx, STM32F207xx
110/163
Doc ID 15818 Rev 7
Equation 1: RAIN max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
fS
(4)
Sampling rate
(fADC = 30 MHz)
12-bit resolution
Single ADC
--
2
Msps
12-bit resolution
Interleave Dual ADC
mode
--
4
Msps
12-bit resolution
Interleave Triple ADC
mode
--
6
Msps
IVREF+
(4)
ADC VREF DC current
consumption in conversion mode
fADC = 30 MHz
3 sampling time
12-bit resolution
-
300
500
A
fADC = 30 MHz
480 sampling time
12-bit resolution
--
TBD
A
IDDA
(4)
ADC VDDA DC current
consumption in conversion mode
fADC = 30 MHz
3 sampling time
12-bit resolution
-1.6
1.8
mA
fADC = 30 MHz
480 sampling time
12-bit resolution
--
TBD
1.
TBD stands for “to be defined”.
2.
If IRROFF is set to VDD, this value can be lowered to 1.65 V when the device operates in a reduced temperature range.
3.
It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.
4.
Based on characterization, not tested in production.
5.
VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
6.
RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.
7.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 61.
Table 61.
ADC characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R
AIN
k0.5
–
()
f
ADC
C
ADC
2
N
2
+
()
ln
×
--------------------------------------------------------------
R
ADC
–
=
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