
General-purpose timers
STM32W108CB, STM32W108HB
Doc ID 16252 Rev 3
10.2
Interrupts
Each timer has its own ARM Cortex-M3 vectored interrupt with programmable priority.
Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and
Several kinds of timer events can generate a timer interrupt, and each has a status flag in
the INT_TIMxFLAG register to identify the reason(s) for the interrupt:
●
INT_TIMTIF - set by a rising edge on an external trigger, either edge in gated mode
●
INT_TIMCCRyIF -set by a channel y input capture or output compare event
●
INT_TIMUIF - set by an update event
Clear bits in INT_TIMxFLAG by writing a 1 to their bit position. When a channel is in capture
mode, reading the TIMx_CCRy register will also clear the INT_TIMCCRyIF bit.
The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request
an ARM Cortex-M3 timer interrupt. Only the events whose bits are set to 1 in
INT_TIMxCFG can do so.
If an input capture or output compare event occurs and its INT_TIMMISSCCyIF is already
set, the corresponding capture/compare missed flag is set in the INT_TMRxMISS register.
Clear a bit in the INT_TMRxMISS register by writing a 1 to it.
OCy
External
Output compare: TIMxCy when used as an output. Same as
OCyREF but includes possible polarity inversion.
OCyREF
Internal
Output compare reference: always active high, but may be
inverted to produce OCy.
PCLK
External
Peripheral clock connects to CK_INT and used to clock input
filtering. Its frequency is 12MHz if using the 24MHz crystal
oscillator and 6Mhz if using the 12MHz RC oscillator.
TIy
Internal
Timer input: TIMxCy when used as a timer input.
TIyFPy
Internal
Timer input after filtering and polarity selection.
TIMxCy
Internal
Timer channel at a GPIO pin: can be a capture input (ICy) or
a compare output (OCy).
TIMxCLK
External
Clock input (if selected) to the external trigger signal (ETR).
TIMxMSK
External
Clock mask (if enabled) AND'ed with the other timer's
TIMxCLK signal.
TRGI
Internal
Trigger input for slave mode controller.
Table 26.
Timer signal descriptions (continued)
Signal
Internal/external
Description