参数资料
| 型号： | TC835CBU |
| 厂商： | Microchip Technology |
| 文件页数： | 10/26页 |
| 文件大小： | 0K |
| 描述： | IC ADC 4 1/2DGT BCD 64-MQFP |
| 标准包装： | 84 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | BCD |
| 数字或字符： | A/D，4.5 位数字 |
| 电流 - 电源： | 1mA |
| 电源电压： | 4 V ~ 6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-BQFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
TC835
5.2
STROBE Output
Integrator
Output
Signal
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur
System Integrate
Zero 10,000
10,001 Counts
Counts (Fixed)
Reference
Integrate
20,001
Counts (Max)
in the center of the digit drive signals (D 1 , D 2 , D 3 , D 5 )
(see Figure 5-3 ).
Busy
Overrange when
Applicable
Underrange when
Applicable
Full Measurement Cycle
40,002 Counts
Expanded Scale Below
D 5 (MSD) goes high for 201 counts when the measure-
ment cycles end. In the center of the D 5 pulse, 101
clock pulses after the end of the measurement cycle,
the first STROBE occurs for one-half clock pulse. After
the D 5 digit strobe, D 4 goes high for 200 clock pulses.
The STROBE goes low 100 clock pulses after D 4 goes
high. This continues through the D 1 digit drive pulse.
The digit drive signals will continue to permit display
Digit Scan
D5
D4
D3
D2
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will
not continue if the previous signal resulted in an
overrange condition.
STROBE
100
Counts
D1
* First D5 of System Zero and
Reference Integrate One Count
Longer
The active low STROBE pulses aid BCD data transfer
to UARTs, processors and external latches.
Digit Scan
for Overrange
* D5
Auto-Zero
Signal
Integrate
*
Reference
Integrate
TC835
Outputs
Busy
End of Conversion
D4
D3
B1 B8
*
D5
(MSD)
Data
D4
Data
D3
Data
D2
Data
D1
(LSD)
Data
D5
Data
D2
D1
STROBE
200
Counts
Note Absence
of STROBE
FIGURE 5-2:
Timing Diagrams for
D5
201
Counts
200
Counts
Outputs.
5.1 RUN/HOLD Input
When left open, this pin assumes a logic " 1 " level. With
a RUN/HOLD = 1 , the TC835 performs conversions
continuously, with a new measurement cycle beginning
every 40,002 clock pulses.
When RUN/HOLD changes to a logic " 0 ," the measure-
D4
D3
D2
D1
200
Counts
200
Counts
200
Counts
200
Counts
ment cycle in progress will be completed, and data held
and displayed as long as the logic " 0 " condition exists.
* Delay between Busy going Low and First STROBE pulse is
dependent on Analog Input.
A positive pulse (> 300 ns) at RUN/HOLD initiates a
FIGURE 5-3:
Strobe Signal Low Five
new measurement cycle. The measurement cycle in
progress when RUN/HOLD initially assumed the logic
Times Per Conversion.
" 0 " state must be completed before the positive pulse
can be recognized as a single conversion run
5.3
BUSY Output
command.
The new measurement cycle begins with a
10,001-count auto zero phase. At the end of this phase,
the busy signal goes high.
DS21478C-page 10
At the beginning of the signal integration phase, BUSY
goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic " 0 " state after the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginning of the measurement cycle,
which starts with the auto zero cycle.
? 2007 Microchip Technology Inc.
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