参数资料
| 型号： | TC835CBU |
| 厂商： | Microchip Technology |
| 文件页数： | 7/26页 |
| 文件大小： | 0K |
| 描述： | IC ADC 4 1/2DGT BCD 64-MQFP |
| 标准包装： | 84 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | BCD |
| 数字或字符： | A/D，4.5 位数字 |
| 电流 - 电源： | 1mA |
| 电源电压： | 4 V ~ 6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-BQFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
TC835
+IN
SW I
Analog
Input Buffer
+ R INT
C INT
+IN
SW I
Analog
Input Buffer
+ R INT
C INT
-
C SZ
–
C SZ
To
SW R
–
Integrator –
SW R
REF
IN
SW Z
C REF
SW IZ SW Z
SW Z
-
+
Integrator
Comparator
+
-
Digital
Section
REF
IN
SW Z
C REF
SW IZ SW Z
SW Z
+
Comparator
+
To
Digital
Section
Analog
Common
SW I
IN
FIGURE 3-2:
SW 1
Switch Open
Switch Closed
System Zero Phase.
Analog
Common
SW I
IN
FIGURE 3-4:
SW 1
Switch Open
Switch Closed
Reference Voltage
3.2.2
ANALOG INPUT SIGNAL
Integration Cycle.
INTEGRATION
3.2.4
INTEGRATOR OUTPUT ZERO
The TC835 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range (-1V
from either supply rail, typically). The input signal polar-
ity is determined at the end of this phase (see
Analog
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the
true system offset voltages are compensated for. This
phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles (see Figure 3-5 ).
Analog
+IN
SW I
Input Buffer
+
R INT
C INT
+IN
SW I
Input Buffer
+
R INT
C INT
–
C SZ
–
C SZ
SW R
REF
IN
SW Z
C REF
SW IZ SW Z
SW Z
–
+
Integrator
Comparator
+
– To
Digital
Section
SW R
REF
IN
SW Z
C REF
SW IZ SW Z
SW Z
–
+
Integrator
Comparator
+
– To
Digital
Section
Analog
Common
SW I
IN
FIGURE 3-3:
SW 1
Switch Open
Switch Closed
Input Signal Integration
Analog
Common
SW I
IN
FIGURE 3-5:
SW 1
Switch Open
Switch Closed
Integrator Output Zero
Phase.
3.2.3
REFERENCE VOLTAGE
Phase.
INTEGRATION
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero (see Figure 3-4 ). The digital read-
ing displayed is:
Reading = 10,000
[Differential Input]
V REF
TABLE 3-6:
INTERNAL ANALOG GATE STATUS
Conversion Cycle Phase
System Zero
Input Signal Integration
Reference Voltage Integration
Integrator Output Zero
SW I
—
Closed
—
—
SW RI +
—
—
Closed*
—
SW RI -
—
—
—
—
SW Z
Closed
—
—
—
SW R
Closed
—
—
—
SW 1
Closed
—
Closed
Closed
SW IZ
—
—
—
Closed
Reference Figures
*Note:
Assumes a positive polarity input signal. SW RI would be closed for a negative input signal.
? 2007 Microchip Technology Inc.
DS21478C-page 7
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