参数资料
| 型号： | TC835CBU |
| 厂商： | Microchip Technology |
| 文件页数： | 6/26页 |
| 文件大小： | 0K |
| 描述： | IC ADC 4 1/2DGT BCD 64-MQFP |
| 标准包装： | 84 |
| 显示器类型： | LED |
| 配置： | 7 段显示 |
| 接口： | BCD |
| 数字或字符： | A/D，4.5 位数字 |
| 电流 - 电源： | 1mA |
| 电源电压： | 4 V ~ 6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-BQFP |
| 供应商设备封装： | 64-PQFP（14x14） |
| 包装： | 管件 |
TC835
3.0
DETAILED DESCRIPTION
(All Pin Designations Refer to 28-Pin DIP)
Analog Input
Signal
Integrator
-
Comparator
3.1
Dual Slope Conversion Principles
+
-
+
The TC835 is a dual slope, integrating analog-to-digital
converter. An understanding of the dual slope
Switch
conversion technique will aid in following the detailed
TC835 operational theory.
The conventional dual slope converter measurement
REF
Voltage
Drive
Polarity Control
Phase
Control
Control
Logic
Clock
cycle has two distinct phases:
1.
Input signal integration.
Display
Counter
2. Reference voltage integration (de-integration).
The input signal being converted is integrated for a
fixed time period, with time being measured by
V IN
V IN
≈ V REF
≈ 1/2 V REF
counting clock pulses. An opposite polarity constant
reference voltage is then integrated until the integrator
output voltage returns to zero. The reference
integration time is directly proportional to the input
Fixed
Signal
Integrate
Time
Variable
Reference
Integrate
Time
signal.
FIGURE 3-1:
Basic Dual Slope Converter.
In a simple dual slope converter, a complete
conversion requires the integrator output to "ramp-up"
3.2
Operational Theory
------------------------ ∫ INT V IN ( T ) DT = --------------------------------
and "ramp-down."
A simple mathematical equation relates the input sig-
nal, reference voltage and integration time:
EQUATION 3-1:
1 T V REF T DEINT
R INT C INT 0 R INT C INT
The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal two
phase dual slope measurement cycle. Reduced
system errors, fewer calibration steps and a shorter
overrange recovery time result.
The TC835 measurement cycle contains four phases:
1. System zero.
Where:
2.
Analog input signal integration.
V REF
=
Reference voltage
3.
4.
Reference voltage integration.
Integrator output zero.
T INT
T DEINT
=
=
Signal integration time (fixed)
Reference voltage integration
time (variable)
Internal analog gate status for each phase is shown in
3.2.1
SYSTEM ZERO
For a constant V IN :
EQUATION 3-1:
V REF T DEINT
V IN = --------------------------------
t INT
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods. Integrating ADCs are immune to the large
conversion errors that plague successive approxima-
tion converters in high noise environments (see
DS21478C-page 6
During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging C AZ (auto zero capacitor) with a compensat-
ing error voltage. With a zero input voltage the
integrator output will remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SW I switches. The
internal input points connect to ANALOG COMMON.
The reference capacitor charges to the reference
voltage potential through SW R . A feedback loop,
closed around the integrator and comparator, charges
the C AZ capacitor with a voltage to compensate for
buffer amplifier, integrator and comparator offset
voltages (see Figure 3-2 ).
? 2007 Microchip Technology Inc.
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