参数资料
型号: TDA9989ET
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封装: 4.50 X 4.50 MM, 0.80 MM HEIGHT, PLASTIC, SOT-962-3, TFBGA-64
文件页数: 14/48页
文件大小: 226K
代理商: TDA9989ET
TDA9989_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 11 June 2009
21 of 48
NXP Semiconductors
TDA9989
HDMI 1.3a transmitter with CEC support
Remark: Gamut-related metadata is an HDMI 1.3a feature.
7.7 Downsampler
This block works only with YCbCr input format; the lters downsample the Cb and Cr
signals by a factor of 2. A delay is added on the Y channel, which corresponds to the
pipeline delay of the lters, to put the Y channel in phase with the Cb-Cr channel.
7.8 Audio input format
TDA9989 is compatible with the following audio features described in the HDMI 1.3a
specication:
S/PDIF
I2S-bus up to two stereo channels
The TDA9989 can carry audio in I2S-bus format (one stereo to two stereo channels) or in
S/PDIF format through one audio pin named AP1. S/PDIF or I2S-bus format can be
selected via the I2C-bus. Only one audio format can be used at a time: either S/PDIF or
I2S-bus. Table 16 shows the audio port allocation and Section 7.8.3 gives more details.
All audio ports are LV-CMOS 1.8 V compatible and LV-CMOS 3.3 V tolerant. It is possible
to map an internally unused port to internal ground via I2C-bus with ENA_AP register on
page 00h for both audio and clock inputs.
7.8.1 S/PDIF
In this format TDA9989 supports 2-channel uncompressed PCM data (IEC 60958) layout
0, or compressed bit stream up to 8 multi channels (Dolby Digital, DTS, AC3 etc.) layout 1.
The TDA9989 is able to recover the original clock from the S/PDIF signal (no need of
external clock).
7.8.2 I2S-bus
There is one I2S-bus stereo input, which enables 2 uncompressed audio channels to be
carried. The I2S-bus input interface receives an I2S-bus signal including serial data, word
select and serial clock.
Typical waveforms for the I2S-bus signals at 64fs are given by Figure 13.
Table 16.
Audio port conguration
Audio port
Input conguration
S/PDIF
I2S-bus
AP0
-
WS (word select)
AP1
S/PDIF input
I2S-bus channel 0
ACLK
-
SCK (I2S-bus clock)
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