参数资料
型号: TDA9989ET
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封装: 4.50 X 4.50 MM, 0.80 MM HEIGHT, PLASTIC, SOT-962-3, TFBGA-64
文件页数: 18/48页
文件大小: 226K
代理商: TDA9989ET
TDA9989_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 11 June 2009
25 of 48
NXP Semiconductors
TDA9989
HDMI 1.3a transmitter with CEC support
As long as the receiver is connected to the transmitter and powered-up, bit RXS_FIL is set
to logic 1.
As soon as the cable is unplugged or receiver side powered off (assuming in this case that
VCC is switched off), the RxSense generates an interrupt inside the TDA9989, changing
the value of bit RXS_FIL to logic 0 (See Table 19). This allows the application to stop
sending unnecessary video content.
This feature is very useful when the receiver recovers from an off-state and does not
generate a HPD transition HIGH-to-LOW-to-HIGH. In this particular case, RxSense will
generate an interrupt so that the chip restarts sending video.
Remark: According to the HDMI specication, only the HPD interrupt allows the
application to read the EDID. The RxSense interrupt is not mandatory to initialize the
EDID reading procedure.
7.11 CEC
TDA9989 with its embedded CEC block provides a complete solution to enable Consumer
Electronic Control (CEC) in product (DSC, DVC, PMP, UM PC). This eliminates the need
of any additional device to handle this feature thus improving BOM (Bill Of Materials).
CEC capability allows AV products (CEC enable) to communicate together over the home
appliance network which could be controlled using only one remote control.
The CEC block manages low level transactions (compliant to CEC timing specication)
over the one bidirectional line It translates CEC protocol in I2C-bus for the host processor
and vice versa. It manages CEC message reception and transmission compliant to CEC
protocol and provides the message to the system micro controller (host processor).
For power consumption optimization purpose CEC could be enable or disable through
I2C-bus register.
The following sections describe CEC
Features
Clocking scheme
7.11.1 Features
Receive and transmit CEC messages to host processor
Supports multiple CEC logical addresses
Supports CEC messages up to 16 bytes long
Programmable retry count
Comprehensive arbitration and collision handling
Table 19.
Receiver detection according to averaged terminal voltage
Average voltage
(Vinp_rxs + Vinn_rxs) / 2
bit RXS_FIL: receiver
powered on
bit RXS_FIL: receiver
powered off
V
≥ 975 mV
1
0
895 mV < V < 975 mV
undened
0
V
≤ 895 mV
0
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