参数资料
型号: TDA9989ET
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封装: 4.50 X 4.50 MM, 0.80 MM HEIGHT, PLASTIC, SOT-962-3, TFBGA-64
文件页数: 24/48页
文件大小: 226K
代理商: TDA9989ET
TDA9989_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 11 June 2009
30 of 48
NXP Semiconductors
TDA9989
HDMI 1.3a transmitter with CEC support
The CEC core does not need memory page mechanism due to its reduced number of
registers.
8.3 ID version
The ID version readable via I2C-bus is dened by the concatenation of VERSION_MSB
and VERSION registers.The ID version value is 131h.
8.4 Clock stretching
Clock stretching pauses a transaction by holding the CSCL line LOW. The transaction
cannot continue until the line is released HIGH again.
For example: on the byte level, a device may be able to receive bytes of data at a fast rate,
but needs more time to store a received byte or prepare another byte to be transmitted.
Slaves can then hold the CSCL line LOW after reception and acknowledgment of a byte to
force the master into a wait state until the slave is ready for the next byte transfer.see
Clock stretching must be supported by I2C-bus master especially when CEC feature of
TDA9989 is used. If CEC feature of TDA9989 is not used, I2C-bus master does not need
to support clock stretching.
9.
Input format
In Table 23 the port VPA has been mapped to Cb (YCbCr space)/B (RGB space), VPB
has been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr
(YCbCr space)/R (RGB space).
Table 23.
Input format
L: recommend tied to LOW voltage
Input pins
Signal
RGB
YCbCr
4:4:4
4 : 2 : 2 (semi-planar)
4 : 2 : 2 (ITU 656-like)
Video port A
VPA[0]
Cb[0]/B[0]
B[0]
Cb[0]
Y0[0]
Y1[0]
Cb[0]
Y0[0]
Cr[0]
Y1[0]
VPA[1]
Cb[1]/B[1]
B[1]
Cb[1]
Y0[1]
Y1[1]
Cb[1]
Y0[1]
Cr[1]
Y1[1]
VPA[2]
Cb[2]/B[2]
B[2]
Cb[2]
Y0[2]
Y1[2]
Cb[2]
Y0[2]
Cr[2]
Y1[2]
VPA[3]
Cb[3]/B[3]
B[3]
Cb[3]
Y0[3]
Y1[3]
Cb[3]
Y0[3]
Cr[3]
Y1[3]
VPA[4]
Cb[4]/B[4]
B[4]
Cb[4]
Cb[0]
Cr[0]
L
VPA[5]
Cb[5]/B[5]
B[5]
Cb[5]
Cb[1]
Cr[1]
L
VPA[6]
Cb[6]/B[6]
B[6]
Cb[6]
Cb[2]
Cr[2]
L
VPA[7]
Cb[7]/B[7]
B[7]
Cb[7]
Cb[3]
Cr[3]
L
Video port B
VPB[0]
Y[0]/G[0]
G[0]
Y[0]
Y0[4]
Y1[4]
Cb[4]
Y0[4]
Cr[4]
Y1[4]
VPB[1]
Y[1]/G[1]
G[1]
Y[1]
Y0[5]
Y1[5]
Cb[5]
Y0[5]
Cr[5]
Y1[5]
VPB[2]
Y[2]/G[2]
G[2]
Y[2]
Y0[6]
Y1[6]
Cb[6]
Y0[6]
Cr[6]
Y1[6]
VPB[3]
Y[3]/G[3]
G[3]
Y[3]
Y0[7]
Y1[7]
Cb[7]
Y0[7]
Cr[7]
Y1[7]
VPB[4]
Y[4]/G[4]
G[4]
Y[4]
Y0[8]
Y1[8]
Cb[8]
Y0[8]
Cr[8]
Y1[8]
VPB[5]
Y[5]/G[5]
G[5]
Y[5]
Y0[9]
Y1[9]
Cb[9]
Y0[9]
Cr[9]
Y1[9]
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