参数资料
型号: TDA9989ET
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封装: 4.50 X 4.50 MM, 0.80 MM HEIGHT, PLASTIC, SOT-962-3, TFBGA-64
文件页数: 21/48页
文件大小: 226K
代理商: TDA9989ET
TDA9989_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 11 June 2009
28 of 48
NXP Semiconductors
TDA9989
HDMI 1.3a transmitter with CEC support
7.12.3 DDC-bus channel
The DDC-bus pins DSDA and DSCL are 5 V tolerant and can work at standard mode
(100 kHz). The DDC-bus is used as a master interface when reading the EDID.
When the device is power-off DSDA and DSCL ports:
become in high-impedance
can withstand 5 V from the sink.
7.13 E-EDID
7.13.1 E-EDID reading
As a master interface for the EDID process, the DDC-bus is compliant with the I2C-bus
specication and has the possibility of repeat/start condition to enable quick access to the
EDID content, as well as the possibility of reading a large EDID (with the use of segment
pointer).
The TDA9989 has a whole I2C-bus page (page 09h) dedicated to the EDID where one
block can be stored. The block can be read by the microprocessor to determine the
supported video and audio format of the downstream site.
Remark: When the block is read by the TDA9989, it generates an interrupt to warn the
main processor that the chip is ready to transmit the content. Once the content is read out
by the main processor, it can allow other blocks to be read if required.
7.13.2 HDMI and DVI receiver discrimination
This information is located in the E-EDID receiver part, in the ‘vendor-specic data block’
within the rst CEA EDID timing extension.
If the 24-bit IEEE Registration Identier contains the value 00 0C03h, then the receiver will
support HDMI, otherwise the device will be treated as a DVI device.
However, even through the TDA9989 have directly access to that information, it is the task
of the micro controller to ask to switch from DVI to HDMI mode.
10009 times
100110 times
others
reserved
Table 20.
Pixel repetition …continued
PR[3]
PR[2]
PR[1]
PR[0]
Pixel repetition factor
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