参数资料
型号: TDA9989ET
厂商: NXP SEMICONDUCTORS
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封装: 4.50 X 4.50 MM, 0.80 MM HEIGHT, PLASTIC, SOT-962-3, TFBGA-64
文件页数: 22/48页
文件大小: 226K
代理商: TDA9989ET
TDA9989_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 11 June 2009
29 of 48
NXP Semiconductors
TDA9989
HDMI 1.3a transmitter with CEC support
8.
I2C-bus interface and register denitions
8.1 I2C-bus protocol
The I2C-bus pins CSDA and CSCL are 1.8 V and 3.3 V tolerant. Both Fast-mode
(400 kHz) and Standard-mode (100 kHz) are supported.
The registers of the TDA9989 can be accessed via the I2C-bus. All registers are R/W
except for those which are condential.
HDMI and CEC cores I2C-bus addresses are given in Table 21 and Table 22.
For read access, the master writes the address of the TDA9989 HDMI or CEC core, and
the subaddress to access the specic register and then the data.
8.2 Memory page management
The I2C-bus memory is split into several pages for HDMI core only, and the selection
between pages is made with common register CURPAGE_ADR. It is only necessary to
write in this register once to change the current page. So multiple read or write operations
in the same page need a write register CURPAGE_ADR once at the beginning.
The following memory pages are available for the TDA9989:
Page 00h: general control
Page 02h: PLL settings
Page 09h: EDID control page
Page 10h: information frames and packets
Page 11h: audio settings and content info packets
Page 13h: gamut-related metadata packets
Table 21.
HDMI core I2C-bus address
HDMI core address
A6
A5
A4
A3
A2
A1
A0
R/W
11100000/1
Table 22.
CEC core I2C-bus address
CEC core address
A6
A5
A4
A3
A2
A1
A0
R/W
01101000/1
Fig 17. I2C-bus access
001aaf292
123456789123456789123456789
SLAVE ADDRESS
SUBADDRESS
SCL
SDA
DATA
STOP
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