- 您现在的位置：买卖IC网 > PDF目录68418 > TLC320AD50IDWR (TEXAS INSTRUMENTS INC) SPECIALTY ANALOG CIRCUIT, PDSO28 PDF资料下载
参数资料
| 型号： | TLC320AD50IDWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | PLASTIC, SO-28 |
| 文件页数： | 3/55页 |
| 文件大小： | 506K |
| 代理商： | TLC320AD50IDWR |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页
1–4
1.4
Ordering Information
PACKAGE
TA
SMALL OUTLINE
PLASTIC DIP
(DW)
QUAD FLAT PACK
(PT)
0
°C to 70°C
TLC320AD50CDW
TLC320AD52CDW
TLC320AD50CPT
TLC320AD52CPT
–40
°C to 85°C
TLC320AD50IDW
1.5
Terminal Functions
TERMINAL
NAME
NO.
PT
NO.
DW
I/O
DESCRIPTION
ALTDATA
17
14
I
Alternate data. ALTDATA signals are routed to DOUT during secondary communication if the phone mode
is enabled using control 2 register.
AUXM
48
4
I
Inverting input to auxiliary analog input. AUXM requires an external single-pole antialias filter with a low output
impedance and should be tied to AVSS if not used.
AUXP
47
3
I
Noninverting input to auxiliary analog input. AUXP requires an external single-pole antialias filter with a low
output impedance and should be tied to AVSS if not used.
AVDD
37
25
I
Analog ADC power supply (5 V only) (see Note 1)
AVDD(PLL)
5
7
I
Analog power supply for the internal PLL (5 V only) (see Note 1)
AVSS
39
26
I
Analog ground (see Note 1)
AVSS(PLL)
7
8
I
Analog ground for the internal PLL (see Note 1)
DIN
15
12
I
Data input. DIN receives the DAC input data and register data from the external DSP (digital signal processor)
and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at
high impedance when FS is not active.
DOUT
14
11
O
Data output. DOUT transmits the ADC output bits and register data, and is synchronized to SCLK. Data is
sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not activated.
When configured as a master, DOUT is active only during the appropriate time slot. DOUT is in high
impedance during the frame syncs for the slaves.
DVDD
11
9
I
Digital power supply (5 V or 3 V) (see Note 1)
DVSS
12
10
I
Digital ground (see Note 1)
FC
23
17
I
Hardware secondary communication request. When FC is set to high, a secondary communication, followed
by the primary communication, will occur to transfer data between this device and the external controller. FC
is sampled and latched on the rising edge of FS at the end of the primary serial communication. See section
3 for details.
FILT
43
28
O
Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 3.2 V. The optimal
capacitor value is 0.1
F (ceramic). This voltage node should be loaded only with a high-impedance dc load.
FLAG
16
13
O
Output flag. During phone mode, FLAG contains the value set in control 2 register.
FS
27
20
I/O
Frame sync. FS is an output when the device is configured as a master (M/S pin tied high). FS is an input when
the device is configured as a slave (M/S pin tied low). When configured as a slave, data will transfer when
FS goes low. FS is internally generated in the master mode for the master device and all slave devices. In
the master mode FS is low during data transfer.
FSD
28
21
O
Frame sync delayed output. The FSD (active-low) output synchronizes a slave device to the frame sync of
the master device. FSD is applied to the slave FS input and is the same duration as the master FS signal but
is delayed in time by the number of shift clocks programmed in the control 3 register.
INM
2
6
I
Inverting input to analog modulator. INM requires an external single-pole antialias filter with a low output
impedance.
INP
1
5
I
Noninverting input to analog modulator. INP requires an external single-pole antialias filter with a low output
impedance.
NOTES:
1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer
should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).
相关PDF资料 |
PDF描述 |
|---|---|
| TLE4935-2LS | SPECIALTY ANALOG CIRCUIT, PSIP3 |
| TLE4905LS | SPECIALTY ANALOG CIRCUIT, PSIP3 |
| TLE4935LS | SPECIALTY ANALOG CIRCUIT, PSIP3 |
| TPD3F303DQDR | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| TPS2010DR | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLC320AD50IPT | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CDW | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:PCM 数据接口:PCM 音频接口 分辨率（位）:15 b ADC / DAC 数量:1 / 1 三角积分调变:是 S/N 比，标准 ADC / DAC (db):- 动态范围，标准 ADC / DAC (db):- 电压 - 电源，模拟:2.7 V ~ 3.3 V 电压 - 电源，数字:2.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-VFBGA 供应商设备封装:80-BGA MICROSTAR JUNIOR（5x5） 包装:带卷 (TR) 其它名称:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
发布紧急采购，3分钟左右您将得到回复。