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参数资料
| 型号： | TLC320AD50IDWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | PLASTIC, SO-28 |
| 文件页数： | 9/55页 |
| 文件大小： | 506K |
| 代理商： | TLC320AD50IDWR |
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2–2
SCLK
FS
DOUT
(16-Bit)
DOUT
(15+1-Bit)
16 SCLKs
MSB
LSB
D15
D14
D1
D0
M/S
1
2
15
16
17
NOTES: A. The 16-bit or (15 + 1)-bit mode is programmed via control register 2.
B. M/S is used to indicate whether the 15-bit data comes from master device or slave device. (Master: M/S = 1, Slave M/S = 0)
C. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edge of SCLK #1, the last bit (D0,M/S) is stable
at the falling edge of SCLK #16.
Figure 2–1. Timing Sequence of ADC Channel (Primary Communication Only)
FS
DOUT
(16-Bit)
16 SCLKs
16-Bit ADC Data
M/S + Register Address +
Register Data/
M/S + Register Address +
All 0s (see Note A)
16 SCLKs
Primary
Secondary
Primary
DOUT
(15 +1-Bit)
15-Bit ADC Data
+ M/S
M/S + Register Data/
M/S + All 0 (see Note A)
128 SCLKs
256 SCLKs
NOTE A: M/S bit (DS15) in the secondary communication is used to indicate whether the register data (address and content) comes from the
master device or the slave device if the read bit is set. During register read operations, bits DS7 – DS0 are the contents of the specified
register. In register write operations, bits DS7 – DS0 are all 0s.
Figure 2–2. Timing Sequence of ADC Channel (Primary and Secondary Communication)
2.1.3
DAC Signal Channel
DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications interval.
These 16-bit digital words, representing the analog output signal before PGA, are clocked into the serial port (DIN)
at the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one word for each primary
communication interval (256 SCLKs). The data are converted to a pulse train by the sigma-delta DAC, which consists
of a digital interpolation filter and a digital modulator. The output of the modulator is then passed to an internal
low-pass filter to complete the analog signal reconstruction. Finally, the resulting analog signal is applied to the input
of a programmable-gain amplifier, which is capable of driving a 600-
load differentially at OUTP and OUTM. The
timing sequence is shown in Figure 2–3.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TLC320AD50IPT | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CDW | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:PCM 数据接口:PCM 音频接口 分辨率（位）:15 b ADC / DAC 数量:1 / 1 三角积分调变:是 S/N 比，标准 ADC / DAC (db):- 动态范围，标准 ADC / DAC (db):- 电压 - 电源，模拟:2.7 V ~ 3.3 V 电压 - 电源，数字:2.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-VFBGA 供应商设备封装:80-BGA MICROSTAR JUNIOR（5x5） 包装:带卷 (TR) 其它名称:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
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