TMP19A43
Bit
31
Mnemonic
Str
Field name
Channel start
Description
Start (initial value:–)
Starts channel operation. If this bit is set to 1, the channel goes into a standby
mode and starts to transfer data in response to a transfer request.
Only a write of 1 is valid to the Str bit and a write of 0 is ignored. A read always
returns a 0.
1: Starts channel operation
This is a reserved bit. Always set this bit to "0."
Normal Completion Interrupt Enable (initial value: 1)
1: Normal completion interrupt enable
0: Normal completion interrupt disable
Abnormal Completion Interrupt Enable (initial value: 1)
1: Abnormal completion interrupt enable
0: Abnormal completion interrupt disable
This is a reserved bit. Although its initial value is "1," always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
Big Endian (initial value: 1)
1: A channel operates by big-endian
0: A channel operates by little-endian
This is a reserved bit. Always set this bit to "0."
This is a reserved bit. Always set this bit to "0."
External Request Mode (initial value: 0)
Selects a transfer request mode. (only for 0ch and 4ch)
1: External transfer request (interrupt request or external DREQn request)
0: Internal transfer request (software initiated)
Positive Edge (initial value: 0)
The effective level of the transfer request signal INTDREQn or DREQn is
specified. This function is valid only if the transfer request is an external transfer
request (if the ExR bit is 1). If it is an internal transfer request (if the ExR bit is
0), the PosE value is ignored. Because the INTDREQn and DREQn signals are
active at "L" level, make sure that this PosE bit is set to "0."
1: Setting prohibited
0: The falling edge of the INTDREQn or DREQn signal or the "L" level is
effective. The DACKn is active at "L" level.
Level Mode (initial value: 0)
Specifies which is used to recognize the external transfer request, signal level or
signal change. This setting is valid only if a transfer request is the external
transfer request (if the ExR bit is 1). If the internal transfer request is specified as
a transfer request (if the ExR bit is 0), the value of the Lev bit is ignored. Because
the INTDREQn signal is active at "L" level, make sure that you set the Lev bit to
"1." The state of active DREQn is determined by the Lev bit setting.
1: Level mode
The level of the DREQn signal is recognized as a data transfer request.
(The "L" level is recognized if the PosE bit is 0.
0: Edge mode
A change in the DREQn signal is recognized as a data transfer request.
(A falling edge is recognized if the PosE bit is 0.)
Snoop Request (initial value: 0)
The use of the snoop function is specified by asserting the bus control request
mode. If the snoop function is used, the snoop function of the TX19A processor
core is enabled and the DMAC can use the data bus of the TX19A processor core.
If the snoop function is not used, the snoop function of the TX19A processor core
does not work.
1: Use snoop function (SREQ)
0: Do not use snoop function (GREQ)
24
23
NIEn
(Reserved)
Normal completion
interrupt enable
22
AbIEn
Abnormal
completion interrupt
enable
21
20
19
18
17
Big
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Big-endian
16
15
14
ExR
(Reserved)
(Reserved)
External request
mode
13
PosE
Positive edge
12
Lev
Level mode
11
SReq
Snoop request
TMP19A43 (rev2.0)
10-9
DMA Controller (DMAC)