TMP19A43
11.2.2 Up-counter (UC0) and Up-counter Capture Registers (TB0UCL, TB0UCH)
This is the 16-bit binary counter that counts up in response to the input clock specified by
TB0MOD<TB0CLK1:0>.
UC0 input clock can be selected from either three types -
φ
T1,
φ
T4 and
φ
T16 - of prescaler output clock
or the external clock of the TB0IN0 pin. For UC0, start, stop and clear are specified by
TB0RUN<TB0RUN> and if UC0 matches the TB0RG1H/L timer register, it is cleared to "0" if the
setting is "clear enable." Clear enable/disable is specified by TB0MOD<TB0CLE>.
If the setting is "clear disable," the counter operates as a free-running counter.
The current count value of the UC0 can be captured by reading the TB0UCL and TB0UCH registers.
Note
Make sure that reading is performed in the order of low-order bits followed by
high-order bits.
If UC0 overflow occurs, the INTTB01 overflow interrupt is generated.
TMRB2, TMRB3, TMRB6 and TMRB7 have the two-phase pulse input count function. The two-phase
pulse count mode is activated by TB2RUN<TB2UDCE>. This counter serves as the up-and-down
counter, and is initialized to 0x7FFF. If a counter overflow occurs, the initial value 0x0000 is reloaded.
If a counter underflow occurs, the initial value 0xFFFF count is continued.. When the two-phase pulse
count mode is not active, the counter counts up only.
11.2.3 Timer Registers (TB0RG0H/L, TB0RG1H/L)
These are 16-bit registers for specifying counter values and two registers are built into each channel. If a
value set on this timer register matches that on a UC0 up-counter, the match detection signal of the
comparator becomes active.
To write data to the TB0RG0H/L and TB0RG1H/L timer registers, either a 2-byte data transfer
instruction or a 1-byte data transfer instruction written twice in the order of low-order 8 bits followed by
high-order 8 bits can be used.
TB0RG0 of this timer register is paired with register buffer 0 - a double-buffered configuration.
TB0RG0 uses TB0RUN<TB0RDE> to control the enabling/disabling of double buffering so that if
<TB0RDE>
=
"0," double buffering is disabled and if <TB0RDE>
=
"1," it is enabled. If double
buffering is enabled, data is transferred from register buffer 0 to the TB0RG0 timer register when there
is a match between UC0 and TB0RG1.
The values of TB0RG0H/L and TB0RG1H/L become undefined after a reset so to use a 16-bit timer, it
is necessary to write data to them beforehand. A reset initializes TB0RUN <TB0RDE> to "0" and sets
double buffering to "disable." To use double buffering, write data to the timer register, set <TB0RDE>
to "1" and then write the following data to the register buffers.
TB0RG0 and the register buffers are assigned to the same address: 0xFFFF_F148/0xFFFF_F149. If
<TB0RDE>
=
"0," the same value is written to TB0RG0 and each register buffer; if <TB0RDE>
=
"1,"
the value is only written to each register buffer. To write an initial value to the timer register, therefore,
the register buffers must be set to "disable."
Note) Please rewrite neither TBxRG1 nor TBxRG0 a double buffer unused while the timer is working.
Note) When a double buffer is used, data is not updated while rewriting TBxREG0.
TMP19A43(rev2.0)
11-8
16-bit Timer/Event Counters (TMRBs)