TMP19A43
Table 13-1 Clock Resolution to the Baud Rate Generator
@ = 40MHz
Prescaler output clock resolution
Clear
peripheral
clock
<FPSEL>
Clock gear
value
<GEAR1:0>
Prescaler clock
selection
<PRCK1:0>
φ
T1
φ
T4
φ
T16
φ
T64
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
00(fperiph/16)
01(fperiph/8)
10(fperiph/4)
11(fperiph/2)
fc/2
5
(0.8
μ
s)
fc/2
4
(0.4 us)
fc/2
3
(0.2us)
fc/2
2
(0.1us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8us)
fc/2
4
(0.4us)
fc/2
3
(0.2 us)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8 us)
fc/2
4
(0.4 us)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8 us)
fc/2
5
(0.8 us)
fc/2
4
(0.4 us)
fc/2
3
(0.2 us)
fc/2
2
(0.1 us)
fc/2
5
(0.8 us)
fc/2
4
(0.4 us)
fc/2
3
(0.2 us)
fc/2
5
(0.8 us)
fc/2
5
(0.8 us)
fc/2
4
(0.4 us)
fc/2
7
(3.2
μ
s)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8us)
fc/2
4
(0.4us)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2us)
fc/2
6
(1.6 ms)
fc/2
5
(0.8 us)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8 us)
fc/2
4
(0.4 us)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8 us)
fc/2
4
(0.4 us)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8 us)
fc/2
7
(3.2 us)
fc/2
6
(1.6
μ
s)
fc/2
5
(0.8 us)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2us)
fc/2
6
(1.6
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
12
(102
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
13
(204
μ
s)
fc/2
12
(102
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
14
(410us)
fc/2
13
(204
μ
s)
fc/2
12
(102
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
000 (fc)
100(fc/2)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
12
(102
μ
s)
fc/2
11
(51.2
μ
s)
fc/2
10
(25.6
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
6
(1.6 us)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
6
(1.6 us)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
6
(1.6 us)
fc/2
9
(12.8
μ
s)
fc/2
8
(6.4
μ
s)
fc/2
7
(3.2 us)
fc/2
6
(1.6 us)
110(fc/4)
111(fc/8)
0 (fgear)
000 (fc)
100(fc/2)
110(fc/4)
1 (fc)
111(fc/8)
(Note 1) The prescaler output clock
φ
Tn must be selected so that the relationship "
φ
Tn < fsys/2" is
satisfied (so that
φ
Tn is slower than fsys/2).
(Note 2) Do not change the clock gear while SIO is operating.
(Note 3) The horizontal lines in the above table indicate that the setting is prohibited.
The serial interface baud rate generator uses four different clocks, i.e.,
φ
T1,
φ
T4,
φ
T16 and
φ
T64, supplied from
the prescaler output clock.
13.3.2 Baud Rate Generator
The baud rate generator generates transmit and receive clocks to determine the serial channel transfer
rate.
The baud rate generator uses either the
φ
T1,
φ
T4,
φ
T16 or
φ
T64 clock supplied from the 7-bit prescaler.
This input clock selection is made by setting the baud rate setting register, BR0CR <BR0CK1:0>.
The baud rate generator contains built-in dividers for divide by 1, (N + m/16), and 16 where N is a
TMP19A43(rev2.0)
13-4
Serial Channel (SIO)