TMP19A43
13.3.21 Signal Generation Timing
c
UART Mode:
Receive Side
Mode
9-bit
8-bit with parity
Around the center of the
1st stop bit
Around the center of the
stop bit
Around the center of the
last (parity) bit
Around the center of the
stop bit
8-bit, 7-bit, and 7-bit with parity
Around the center of the 1st stop bit
Interrupt generation
timing
Framing error timing
Around the center
of the 1st stop bit
Around the center
of the stop bit
Around the center of the stop bit
Parity error generation
timing
Overrun error generation
timing
Around the center of the last (parity)
bit
Around the center of the stop bit
Around the center
of the stop bit
Transmit Side
Mode
9-bit
8-bit with parity
Just before the stop bit is
sent
8-bit, 7-bit, and 7-bit with parity
Just before the stop bit is sent
Interrupt generation
timing
(<WBUF> = 0)
Interrupt generation
timing
(<WBUF> = 1)
Just before the stop
bit is sent
Immediately after
data is moved to
send buffer 1 (just
before start bit
transmission)
Immediately after data is
moved to send buffer 1
(just before start bit
transmission)
Immediately after data is moved to
send buffer 1 (just before start bit
transmission)
d
I/O interface mode:
Receive Side
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
rising or falling edge mode, respectively)
SCLK output
mode
transfer to receive buffer 2) or just after receive buffer 2 is read
SCLK input mode Immediately after the rising edge or falling edge of the last SCLK
depending on the rising or falling edge triggering mode,
respectively (right after data is moved to receive buffer 2)
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
rising or falling edge mode, respectively)
Immediately after the rising edge of the last SCLK
Interrupt generation
timing
(WBUF = 0)
Immediately after the rising edge of the last SCLK (just after data
Interrupt generation
timing
(WBUF = 1)
Overrun error
generation timing
Transmit Side
SCLK output
mode
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
rising or falling edge mode, respectively)
SCLK output
mode
data is moved to send buffer 1
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for
the rising or falling edge mode, respectively) or just after data is
moved to send buffer 1
SCLK input mode Immediately after the falling or rising edge of the next SCLK (for
the rising or falling edge triggering mode, respectively)
Immediately after the rising edge of the last SCLK
Interrupt generation
timing
(WBUF = 0)
Immediately after the rising edge of the last SCLK or just after
Interrupt generation
timing
(WBUF = 1)
Under-run error
generation timing
Note 1) Do not modify any control register when data is being sent or received
(in a state ready to send or receive).
Note 2) Do not stop the receive operation (by setting SC0MOD0 <RXE> = "0")
when data is being received.
Note 3) Do not stop the transmit operation (by setting SC0MOD1 <TXE> = "0")
when data is being transmitted.
TMP19A43(rev2.0)
13-21
Serial Channel (SIO)