TMP19A71
Detailed Description of the PMD0 Registers
Symbol
Name
Function
UPDWN
PWM counter flag
Indicates whether the PWM counter is up-counting or down-counting. When edge
PWM is selected, this bit is always read as 0.
Enables the PMD synchronized start function.
Selects whether to make duty setting independently for each phase or to use the
CMPU register setting for all three phases.
Selects whether to generate an interrupt when PWM counter equals 1 or the
MDPRD value.
Selects the PWM interrupt period from 0.5 PWM period, one PWM period, two PWM
periods and four PWM periods. If this bit is changed during operation, an interrupt
may occur at that time.
Selects PWM Mode 0 (edge PWM, sawtooth wave) or PMW Mode 1 (center PWM,
triangular wave).
When this bit is cleared to stop and clear the PWM counter, output ports become
high-impedance. Before setting this bit to 1 to start the PWM counter, it is necessary
to set all the other bits in the MDCR0 register. While this bit is set to 1, do not change
the MDCR0 settings other than the PWMEN bit.
A 16-bit counter for reading the PWM period count value.
A 16-bit register for specifying the PWM period. This register is double-buffered and
can be changed even when the PWM counter is counting. The buffer is loaded at
every PWM period. (That is, when the PWM counter matches the MDPRD value.
When 0.5 PWM period is selected, loading is performed when the PWM counter
matches 1 or MDPRD0.) See Figure 14.3.4.
16-bit compare registers for determining the output pulse width of U, V and W
phases. These registers are double-buffered. Pulse width is determined by
comparing the buffer and the PWM counter to evaluate which is larger. When
CMPx0 = 0, a 0% duty-cycle waveform is generated. When CMPx0 >= MDPRD0, a
100% duty-cycle waveform is generated. (To be loaded when the PWM counter
matches the MDPRD value. When 0.5 period is selected, loading is performed when
the PWM counter matches 1 or MDPRD.)
SYNCEN
DTYMD
PMD synchronized start
Duty mode
PINT
PWM interrupt timing
INTPRD
PWM interrupt period
PWMMD
PWM mode
PWMEN
Waveform generation circuit
enable/disable
MDCNT
MDPRD
PWM counter
PWM period
CMPU
CMPV
CMPW
PWM pulse width
Setting the SYNCEN bit of the MDCR0 register to 1 enables the PMD synchronized start function.
When the PWMEN bit of the MDCR0 is set to 1 with the PMD synchronized start function enabled,
PMD0 is put on standby for starting as soon as the PWMEN bit of the MDCR1 is set to 1 to start PMD1.
By setting the SYNCEN and PWMEN bits simultaneously, PMD0 can be put on standby for synchronized
start.
When the synchronized start function is enabled for both PMD0 and PMD1 (MDCR0.SYNCEN=1,
MDCR1.SYNCEN=1), the channel that is enabled first (MDCRx.PWMEN bit=1) is put on standby and
starts operating as soon as the other channel is enabled.
Even when the synchronized start function is enabled, registers are set independently for each channel.
To operate PMD0 and PMD1 with the same conditions, it is necessary to set the PMD0 and PMD1
registers identically.
Example: To start PMD0 in synchronization with PMD1
MDCR0 = 0y********_*1*****1
; SYNCEN=1 (Enable the synchronized start function.)
; PWMEN=1 (Put PMD0 on standby.)
; PWMEN=1 (Start PMD1.)
MDCR1 = 0y********_*******1
TMP19A71
14-9