TMP19A71
TMP19A71
7-14
7.8.6.2
Initial Settings Specific to Each Interrupt Source
The registers that must be set for using an interrupt varies by sources shown below:
Table 7.8.5 Interrupt Detection and Setting Register
Interrupt Type
Setting Regiser
Supported Interrupt Sensitivity Settings
(1) External pin interrupts
INT0 to INT3
PxIER (Port)
PxFR (Port)
CLKINTx (CG)
IMRxx (INTC)
PxIER (Port)
PxFR (Port)
IMRxx (INTC)
PxIER (Port)
PxFR (Port)
PxECR (Port)
EMGCRx (PMD)
IMRxx (INTC)
P9IER (Port)
P9FR2 (Port)
P9ECR (Port)
IMR33 (INTC)
IMRxx (INTC)
Programmable as low level, high level, falling edge, or rising edge
sensitive through the IxSEN field of the CLKINTx register in the CG. In the
INTC, the EIMxx field of the IMRxx register must be set to falling edge or
low level according to the setting made in the CG.
Programmable as low level, high level, falling edge, or rising edge
sensitive through the EIMxx field of the IMRxx register in the INTC.
(2) External pin interrupts
INT4 to INT9
(3) Emergency stop interrupts
INTEMGx
Programmable as low level, high level, falling edge, or rising edge
sensitive through the ERMx field of the PxECR register in the port unit. In
the INTC, the EIMxx field of the IMRxx register must be set to falling edge.
(4) Emergency stop interrupt
INTTBE0
Programmable as low level, high level, falling edge, or rising edge
sensitive through the ERM9 field of the P9ECR register in the port unit. In
the INTC, the EIM33 field of the IMR33 register must be set to falling edge
or low level.
Must always be set as falling edge sensitive.
(5) Other interrupts
Note: In level detection, a value is checked at internal clock timing each time. An edge is detected by
comparing a previous value with a current value at internal clock timing.
1.
External Pin Interrupts, INT0 to INT3
In the port unit, set the PxIER register to enable input (see 7. Port Function).
In the port unit, set INT0 to INT3 as the pin function to the PxFR register (see 7.
Port Function).
In the CG, set Interrupt Sensitivity in the IxSEN field of the CLKINTx register (see
5.3.3 Interrupt Registers).
In the CG, set Enable/Disable of Standby Cancel in the IxKI bit of the CLKINTx
register (see 5.3.3 Interrupt Registers).
In the INTC, set the EIMxx field of the IMRxx register to specify the sensitivity of
the interrupt signal sent from the CG. When rising/falling edge is selected in the
CLKINTx.IxSEN, set 10 to the IMRxx.EIMxx to select falling edge. When high/low
level is selected in the CLKINTx.IxSEN, set 00 to the IMRxx.EIMxx to select low
level (see 7.8.10 Register ).
Note 1: To write to the CLKINTx register, it is necessary to write 0x5A5A and then 0xF0F0 in the CGACT register.
Note 2: To initialize an interrupt, follow the interrupt detection route indicated in Table 7.8.3 and make the interrupt
enable with the CP0 register. If any different setting order is used, an unexpected interrupt may be generated.
So, be sure to clear interrupt sources before setting interrupt enable. Similarly, to disable an interrupt, make
the interrupt disable with the CP0 register and then set the registers accordingly in the reverse order of
interrupt detection route.