TMP19A71
5)
Auto Chip Erase command
The Auto Chip Erase command requires six bus cycles. The flash area is partitioned into two
blocks, Block 0 and Block 1. The chip erase operation is performed for each individual block.
After completion of the sixth bus cycle, the Auto Chip Erase operation will commence
immediately. The embedded Auto Erase algorithm automatically preprograms the entire
memory for an all-0 data pattern prior to the erase; then it automatically erases and verifies
the entire memory for an all-1 data pattern. The system can determine the status of the chip
erase operation by using write status flags (see Table 17.4.3). Any commands written during
the chip erase operation are ignored. A hardware reset immediately terminates the chip erase
operation. The chip erase operation that was interrupted should be re-initiated once the flash
memory is ready to accept another command sequence because data may be corrupted.
The block protection feature disables erase operations in any block. The Auto Chip Erase
algorithm erases the unprotected blocks and ignores the protected blocks. If both blocks are
protected, the Auto Chip Erase command does nothing; the flash memory returns to Read
mode in approximately 100
μ
s after the completion of the sixth bus cycle of the command
sequence. When the embedded Auto Chip Erase algorithm is complete, the flash memory
returns to Read mode.
If any failure occurs during the erase operation, the flash memory remains locked in
Embedded Operation mode. The system can determine this status by using write status flags.
To put the flash memory back in Read mode, use a software reset or a hardware reset to reset
the flash memory or the device. In case of an erase failure, it is recommended to replace the
chip or discontinue the use of the failing flash block. The failing block can be identified by the
Block Erase command.
6)
Auto Block Erase and Auto Multi-Block Erase Commands
The Auto Block Erase command requires six bus cycles. A time-out begins from the
completion of the command sequence. After a time-out, the erase operation will commence.
The embedded Auto Block Erase algorithm automatically preprograms the selected block for
an all-0 data pattern, and then erases and verifies that block for an all-1 data pattern.
To erase the next block, the sixth bus cycle must be repeated; the next block address and the
Auto Block Erase command must be provided within the time-out period.
Any command other than Auto Block Erase during the time-out period resets the flash
memory to Read mode. The block erase time-out period is 50
μ
s. The system may read DQ3 to
determine whether the time-out period has expired. The block erase timer begins counting
upon completion of the sixth bus cycle of the Auto Block Erase command sequence. The
system can determine the status of the erase operation by using write status flags (see Table
17.4.3).
Any commands written during the block erase operation are ignored. A hardware reset
immediately terminates the block erase operation. The block erase operation that was
interrupted should be re-initiated once the flash memory is ready to accept another command
sequence because data may be corrupted.
The block protection feature disables erase operations in any block. The Auto Block Erase
algorithm erases the unprotected blocks and ignores the protected blocks. If all the selected
blocks are protected, the Auto Block Erase algorithm does nothing; the flash memory returns
to Read mode in approximately 100
μ
s after the final bus cycle of the command sequence.
If any failure occurs during the erase operation, the flash memory remains locked in
Embedded Operation mode. The system can determine this status by using the write status
flags. To put the flash memory back in Read mode, use a software or hardware reset to reset
the flash memory or the whole chip. In case of an erase failure, it is recommended to replace
the chip or discontinue the use of the failing flash block. If any failure occurred during the
TMP19A71
17-54