TMP19A71
TMP19A71
7-3
7.4
Nonmaskable Interrupt (NMI)
A Nonmaskable Interrupt (NMI) occurs when an external NMI pin is asserted as specified by
the NMISEN field of the CLKNMI register; the WDT counts to the NMI value; or the bus error
area is accessed by a store access including DMA transfer when MODECR<BERCTL>=0.
When a NMI occurs, the ERL and NMI bits of the CP0 Status register are set to 1 and a control
jumps to the exception vector address 0xBFC0_0000.
The PC value at the time of an NMI is stored in the CP0 ErrorEPC register. However, if a bus
error occurs during a store instruction, a NMI exception is generated asynchronously to the
instruction execution timing and the PC is stored not at the instruction that caused the NMI
but at the instruction that is being executed when the NMI is generated.
Upon NMI generation, when Shadow Register Set is enabled, SSCR <CSS> will be
overwritten by the value of SSCR <PSS> but the register bank will not be switched because the
value of SSCR <CSS> is not updated. The reason why only the SSCR <PSS> value is updated
is because it is necessary to prevent the register bank from being changed when SSCR <PSS>
is overwritten by the value of SSCR <CSS> due to an ERET instruction executed upon
returning from NMI.
The cause of NMI generation can be determined by NMIFLG <WDT> and <WBER> of CG.
A reset initializes the NMI pin (P95) as a general-purposed port. To use the NMI pin, it is
necessary to set the P9FR15 bit of the Port 9 Function Register 1 (P9FR1) and the NMISEN
field of the CLKNMI register.
For a detailed description of NMI handling, refer to the chapter
“
Exception Handling
Nonmaskable Interrupts
”
of the separate volume, TX19A Core Architecture
7.5
General Exceptions (other than Reset Exception/NMI)
A general exception occurs when a specific instruction such as the SYSCALL instruction is
executed or an error condition such as an illegal instruction fetch is detected. When a general
exception occurs with the Status.BEV bit set to 1, control jumps to the exception vector address
0xBFC0_380. The cause of a general exception can be determined by the ExCode field of the CP0
Cause register.
The PC value at the time of a general exception is stored in the CP0 EPC register. However, a
Bus Error exception (data access) is generated asynchronously to the instruction execution
timing so that the PC is stored not at the instruction that caused the exception but at the
instruction that is being executed when the exception is generated. Upon a general exception,
when the shadow register set is enabled, SSCR <CSS> will be overwritten by the value of SSCR
<PSS> but the register bank will not be switched because the value of SSCR <CSS> is not
updated. The reason why only the SSCR <PSS> value is updated is because it is necessary to
prevent the register bank from being changed when SSCR <PSS> is overwritten by the value of
SSCR <CSS> due to an ERET instruction executed upon returning from the exception.
The illegal address that caused an Address Error exception (instruction fetch, load, store) or
Bus Error exception (instruction fetch, data access) is stored in the CP0 BadVAddr register.
For a detailed description of general exception handling, refer to the chapter
“
Exception
Handling
”
of the separate volume, TX19A Core Architecture
Note 1
: No Address Error exception (load, store) occurs during DMA transfer. In this case, error conditions can
be detected by the configuration error flag (the Conf bit of the CSRx register) in the DMAC.
Note 2
: A Bus Error exception (data access) occurs during a load instruction or a load access by DMA transfer.