参数资料
型号: TMP86CH47SUG
厂商: Toshiba Corporation
英文描述: Zener Diode; Application: General; Pd (mW): 500; Vz (V): 18.1 to 19.0; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述: 8位微控制器
文件页数: 121/160页
文件大小: 1627K
代理商: TMP86CH47SUG
Page 113
TMP86CH47SUG
Figure 10-12 Example of Receive Error Processing
Note: If receive error is not corrected, an interrupt request does not generate after the error occurs.
10.3.3.3 Transmit/receive mode
The transmit/receive mode are selected by writing “10” to SIOCR1<SIOM>.
(1)
Starting the transmit/receive operation
Transmit/receive mode is selected by writing “10B” to SIOCR1<SIOM>. Serial clock is selected
by using SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.
When a transmit data is written to the transmit buffer register (SIOTDB), SIOSR<TXF> is cleared
to “0”.
After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to the falling edge of
SCK
pin.
The data is transferred sequentially starting from SO pin with the direction of the bit specified by
SIOCR1<SIODIR>, synchronizing with the
SCK
pin's falling edge. And receiving operation also
starts with the direction of the bit specified by SIOCR1<SIODIR>, synchronizing with the
SCK
pin's
rising edge.
SIOSR<SEF> is kept in high level between the first clock falling edge of
SCK
pin and eighth clock
falling edge.
SIOSR<TXF> is set to “1” at the rising edge of
SCK
pin after the data written to the SIOTDB is
transferred to shift register. When 8-bit data has been received, the received data is transferred to
SIORDB from shift register, then the INTSIO interrupt request occurs, synchronizing with setting
SIOSR<RXF> to “1”.
Note 1: In internal clock operation, when the SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift
register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
SCK
pin.
Note 2: In external clock operation, when the falling edge is input from
SCK
pin after SIOCR1<SIOS> is
set to "1", SIOTDB is transferred to shift register immediately. When the rising edge is input from
SCK
pin, receive operation also starts.
Reading received
data B
Reading received
data A
B
A7 A6
A
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Start shift
operation
Start shift
operation
Start shift
operation
Write a "0" after reading the
received data when a receive
error occurs.
SIOCR1<SIOS>
SIOSR<SEF>
SCK
pin
SIOSR<RXERR>
INTSIO
interrupt
request
SIORDB
SI pin
SIOSR<SIOF>
SIOSR<RXF>
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