参数资料
型号: TMP86CH47SUG
厂商: Toshiba Corporation
英文描述: Zener Diode; Application: General; Pd (mW): 500; Vz (V): 18.1 to 19.0; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述: 8位微控制器
文件页数: 23/160页
文件大小: 1627K
代理商: TMP86CH47SUG
Page 15
TMP86CH47SUG
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with
RESET
pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bit 0 in SYSCR1 is read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as
STOP
pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
System Control Register 1
SYSCR1
7
6
5
4
3
2
1
0
(0038H)
STOP
RELM
RETM
OUTEN
WUT
(Initial value: 0000 000*)
STOP
STOP mode start
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
R/W
RELM
Release method for STOP
mode
0: Edge-sensitive release
1: Level-sensitive release
R/W
RETM
Operating mode after STOP
mode
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
R/W
OUTEN
Port output during STOP mode
0: High impedance
1: Output kept
R/W
WUT
Warm-up time at releasing
STOP mode
Return to NORMAL mode
Return to SLOW mode
R/W
000
010
100
110
*01
*11
3 x 2
16
/fc
2
16
/fc
3 x 2
14
/fc
2
14
/fc
3 x 2
10
/fc
2
10
/fc
3 x 2
13
/fs
2
13
/fs
3 x 2
6
/fs
2
6
/fs
3 x 2
6
/fs
2
6
/fs
System Control Register 2
SYSCR2
(0039H)
7
6
5
4
3
2
1
0
XEN
XTEN
SYSCK
IDLE
TGHALT
(Initial value: 1000 *0**)
XEN
High-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
R/W
XTEN
Low-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
SYSCK
Main system clock select
(Write)/main system clock moni-
tor (Read)
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
IDLE
CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
R/W
TGHALT
TG control (IDLE0 and SLEEP0
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)
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