参数资料
型号: TMP86CH47SUG
厂商: Toshiba Corporation
英文描述: Zener Diode; Application: General; Pd (mW): 500; Vz (V): 18.1 to 19.0; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述: 8位微控制器
文件页数: 37/160页
文件大小: 1627K
代理商: TMP86CH47SUG
Page 29
TMP86CH47SUG
2.3
Reset Circuit
The TMP86CH47SUG has four types of reset generation procedures: An external reset input, an address trap reset,
a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the
system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the
maximum 24/fc[s] (The
RESET
pin outputs "L" level).
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-
ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5
μ
s at 16.0 MHz) when
power is turned on.
RESET
pin outputs "L" level during maximum 24/fc[s] (1.5
μ
s at 16.0MHz).
Table 2-3 shows on-chip hardware initialization by reset action.
2.3.1
External Reset Input
The
RESET
pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the
RESET
pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt-
age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initial-
ized.
When the
RESET
pin input goes high, the reset operation is released and the program execution starts at the
vector address stored at addresses FFFEH to FFFFH.
Figure 2-15 Reset Circuit
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Initial Value
On-chip Hardware
Initial Value
Program counter
(PC)
(FFFEH)
Prescaler and divider of timing generator
0
Stack pointer
(SP)
Not initialized
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
Not initialized
Jump status flag
(JF)
Not initialized
Watchdog timer
Enable
Zero flag
(ZF)
Not initialized
Output latches of I/O ports
Refer to I/O port circuitry
Carry flag
(CF)
Not initialized
Half carry flag
(HF)
Not initialized
Sign flag
(SF)
Not initialized
Overflow flag
(VF)
Not initialized
Interrupt master enable flag
(IMF)
0
Interrupt individual enable flags
(EF)
0
Control registers
Refer to each of control
register
Interrupt latches
(IL)
0
RAM
Not initialized
Internal reset
RESET
VDD
Malfunction
reset output
circuit
Watchdog timer reset
Address trap reset
System clock reset
相关PDF资料
PDF描述
TMP86CH49FG Zener Diode; Application: General; Pd (mW): 500; Vz (V): 18.8 to 19.7; Condition Iz at Vz (mA): 2; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
TMP86CH72FG Zener Diode; Application: General; Pd (mW): 500; Vz (V): 19.5 to 20.4; Condition Iz at Vz (mA): 2; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
TMP86CK74AFG Zener Diode; Application: General; Pd (mW): 500; Vz (V): 20.2 to 21.1; Condition Iz at Vz (mA): 2; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
TMP86CM23AUG Zener Diode; Application: General; Pd (mW): 500; Vz (V): 20.9 to 21.9; Condition Iz at Vz (mA): 2; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
TMP86CM27FG Zener Diode; Application: General; Pd (mW): 500; Vz (V): 21.6 to 22.6; Condition Iz at Vz (mA): 2; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
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