TOSHIBA
TMPR3904F Rev. 2.0
124
26
13
PosE
Rising edge
Positive Edge
Designates the valid level of the transfer request signal
DREQn. This is valid only when the transfer request is
an external transfer request (the ExR bit is 1). When it is
an internal transfer request (the ExR bit is 0), the value of
the PosE shall be ignored. There are the edge detection
and the level detection as the methods to acknowledge
the DREQn signal; and they are set up in the Lev bit.
The active level of the transfer acknowledge signal
DACKn is the same as the active level of the DREQn
signal.
1: The rising or the high level of the DREQn signal
is valid. The active level of the DACKn signal
is high.
0: The falling or the low level of the DREQn signal
is valid. The active level of the DACKn signal
is low.
Level Mode
Designates the request method of the external transfer
request. This is valid only when an external transfer
request is set up (the ExR bit is 1) as the transfer request.
When an internal transfer request (the ExR bit is 0) is set
up, the value of the Lev bit shall be ignored. The valid
level of the DREQn signal is set up in the PosE bit.
1: Level mode. Acknowledges the levels (the low level
when the PosE bit is 0 and the high level when the PosE
bit is 1) of the DREQn signal as data transfer requests.
0: Edge mode. Acknowledges changes (the falling edge
when the PosE bit is 0 and the rising edge when the PosE
bit is 1) in the DREQn signal as data transfer requests.
SReq (Snoop Request)
Designates whether or not to use the snoop function as
the bus ownership request mode. When using it, the
snoop function of the TX39 Processor Core becomes
valid; and the TX39 Processor Core watches the address
of the DMA transfer. When not using it, the snoop
function of the TX39 Processor Core does not function.
1: Snoop function is used (SREQ).
0: Snoop function is not used (GREQ).
The GREQ is not able to be used in the TX3904F.
12
Lev
Level mode
11
SReq
Snoop request
Fig. 10-6 Channel Control Registers (CCRn) (3/4)