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TOSHIBA
TMPR3904F Rev. 2.0
164
11.3
Functions
11.3.1
Interrupt sources
The TX3904 has the following interrupt sources.
(Maskable) interrupts
Table 11-1 shows the interrupt sources of the TX3904.
The priority of Numbers 0-15 interrupts is arbitrated by the IRC and the interrupt with the
highest priority is informed to the TX39 Processor Core. When one of the Numbers 0-15
interrupts is informed to the TX39 Processor Core, IP[4] in the TX39 Cause register is set and,
as the same time, the interrupt number is indicated in the IP[3:0].
Interrupts by the INT[0] are not arbitrated for the priority unlike the Numbers 0-15 interrupts.
Interrupts by the INT[0] are not masked in the TX3904 internal circuits. When an interrupt by
the INT[0] is informed of, IP[5] is set.
Table 11-1 Interrupt Sources
Interrupt
Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IP[5:0]
Interrupt Request
Source
TMR2
TMR1
TMR0
SIO1
SIO0
DMAC0
DMAC0
DMAC1
DMAC1
INT[7]
INT[6]
INT[5]
INT[4]
INT[3]
INT[2]
INT[1]
INT[0]
Name of Interrupt
x11111
x11110
x11101
x11100
x11011
x11010
x11001
x11000
x10111
x10110
x10101
x10100
x10011
x10010
x10001
x10000
1xxxxx
Timer Interrupt
Timer Interrupt
Timer Interrupt
SIO Interrupt
SIO Interrupt
DMA Interrupt (Ch.0)
DMA Interrupt (Ch.1)
DMA Interrupt (Ch.2)
DMA Interrupt (Ch.3)
External Interrupt
External Interrupt
External Interrupt
External Interrupt
External Interrupt
External Interrupt
External Interrupt
External Interrupt
Non-maskable interrupts
The sources for non-maskable interrupts are divided into the interrupts by the NMI* signal,
watchdog timer interrupts by the TMR2 and bus error in a write operation by the TX39
processor core.
The TX3904 acknowledges falling edges of the NMI* as a non-maskable interrupt request.
The TMR2 requests of the TX39 Coprocessor Core for a non-maskable interrupt if the TMR
requests for a watchdog interrupt in the watchdog timer mode. However, if the WR bit of the
CConR is set to 1, reset is implemented to the TX3904 at a watchdog interrupt time.