TOSHIBA
TMPR3904F Rev. 2.0
138
26
10.4.2 Transfer requests
In order to conduct a data transfer by the DMAC, it is necessary to generate a transfer request to
the DMAC. There are two kinds in the DMAC’s transfer requests--an internal transfer request
and an external transfer request. The transfer requests can be set up for each channel.
For either transfer request, if a transfer request occurs after the channel operation is started, the
DMAC is granted the bus ownership to conduct the data transfer.
Internal transfer request
If “1” is set to the Str bit of the CCR when the ExR bit of the CCRn is 0, a transfer request
occurs immediately. This transfer request is called the internal transfer request.
In the internal transfer request, a transfer request exists until the channel operation has
completed so that data are transferred consecutively unless a shift to a channel whose priority is
higher or a shift of the bus ownership to a bus master whose priority is higher occurs.
External transfer request
When the ExR bit of the CCRn is 1, if a transfer request is informed from the external circuit
through the DREQn signal that supports to the channel after the Str bit of the CCR has been set
to 1 and the channel has become the wait status, a transfer request is generated. This transfer
request is called the external transfer request. The external transfer request is used for the
transfer between a memory and an I/O device.
In the acknowledgment method of the DREQn signal, there are an edge mode that acknowledges
edges and a level mode that acknowledges levels. The polarity of the edge or level that is to be
acknowledged by the PosE bit of the CCRn can be designated.
The data transfer unit for one transfer request is designated in the TrSiz field of the CCRn.
Either 32-bit, 16-bit, or 8-bit can be designated.
In the edge mode, it is necessary at each transfer request to deassert the DREQn signal and then
to assert it to made a valid edge; however, in the level mode, consecutive transfer requests can
be acknowledged by maintaining the valid level.
Do not write “1” into the stop bit in the channel control register during continuous transfer in the
level mode. If it is necessary to suspend a data transfer by the stop bit in the level mode, the
DREQn signal must be asserted and deasserted for each word transferred.
There are two DMAC operation, synchronized to the SYSCLK and to the internal clock
(GCLK). The SYSCLK and GCLK is the same in the full speed bus mode. On the other hand,
it is necessary to take care of the external signals in the half speed bus mode.
- DREQn (input)