TOSHIBA
TMPR3904F Rev. 2.0
68
8.5.4
32/16-bit static bus sizing
Supports the DRAM of 16-bit bus width by setting up 16BUS0 and 16BUS1 of the DCCRn
(n=1,0).
32-bit Bus Access
Indicates that the DRAM connected to the channel is 32-bit bus when the 16BUSn of the
DRAM channel control register is 0. It can conduct the most efficient memory access.
Word/triple-byte access with 16-bit width DRAM
Indicates that the DRAM connected to the channel is 16-bit bus when the 16BUSn of the
DRAM channel control register is 1. At this time, the DRAMC conducts a memory access twice
at the timing set up in the register when a word or triple-byte access is requested. The second
access shall be page mode.
Half-word/byte access with 16-bit width DRAM
If a half-word or byte access is requested when the 16BUSn of the DRAM channel control
register is 1, the DRAMC conducts a memory access once at the timing set up in the register.
8.5.5
Support for external bus master
In the TX3904, the DRAM memory address is multiplexed with the address bus signal. When
the external bus master conducts a memory access using the DRAMC, it is necessary to avoid
conflicts between the DRAM memory address output and the address signal that is output by the
external bus master.
The external bus master is expected to manage not to generate a page hit miss when it uses the
DRAMC. The accessing address must be word (32-bit) boundary. The number of data transfer
in burst mode must be a multiple of 32 bits.
8.5.6
Support for half speed bus
The signals generated for DRAM (address, data, RAS* and CAS*) is synchronized to a rising
edge of a processor clock (internal clock) in half speed bus mode. So these signals are not
synchronized to a rising edge of the SYSCLK.
When the external bus master conducts a memory access through the DRAMC in the half speed
mode, set up a wait in the DRAMC channel control register such that the number of the DRAM
access cycles (the number of GCLK cycles) is an even number.