TOSHIBA
TMPR3904F Rev. 2.0
141
26
Edge Mode
In the edge mode, the internal DREQn signal (dreq) is edge-detected. If the valid edge of the
dreq signal is acknowledged at a rising of the internal clock (GCLK) (if it is presently at the
active level although it was not at the active level at the rising of one GCLK before) when the
channel is in the wait status, the DMAC acknowledges that there is a transfer request and
switches to the transfer status to start the transfer operation. The active edge (falling or rising)
of the DREQn signal is set up in the PosE bit of the CCRn. The active level of the DACKn
signal is at high when a rising of the DREQn signal is on the valid edge, and at low when a
falling of the DREQn signal is on the active edge.
If the valid edge of the dreq signal is acknowledged by a rising of the GCLK that acknowledges
the assertion of the acknowledge signal (which is generated by the on-chip memory controllers
at a memory access in the dual address mode or in the single address mode, or is the same as the
ACK* singal at an I/O access in the dual address mode), the next data transfer is conducted
immediately afterwards. However, if a transfer request is generated on another channel with a
higher priority, a channel transit takes place.
If there is no valid edge of the dreq signal by the rising of the GCLK that acknowledges the
assertion of the acknowledge signal, it is understood that there is no transfer request so that a
transfer operation on another channel may be started or the bus ownership may be released to be
in the wait status.
The acknowledge signal is recognized at the rising edge of the GCLK which precedes the
GCLK cycle when the final LAST* signal for a data transfer is negated.
The unit of the transfer request is designated in the TrSiz field of the CCRn.
SYSCLK
dreq
D R E Q n
(Bus ownership request)
Acknowledge signal
(Bus ownership
release notice)
A[31:1]
A
B E [3:0]*
R/W*
BSTART*
DACKn
Data transfer
Data transfer
The dreq, the bus ownership request signal, the bus ownership release notice signal and the acknowledge
signal are internal signals of the TX3904.
Fig. 10-19 Transfer Request Timing (Edge Mode)