TOSHIBA
TMPR3904F Rev. 2.0
213
13.4.2 Pulse generator mode
When the TMODE of the TCRn (n=2,1) is 1, it is the pulse generator mode. In the pulse
generator mode, quadrangular waves of at-will frequency and duty can be output using two
compare registers--CPRA and CPRB. (The pulse generator mode cannot be used in Timer 0.)
When the TCE of the TCRn is set to 1, the 24-bit counter starts counting. When the value set to
the CPRA and the count value match, the timer flip-flop is reversed. The output of the timer
flip-flop is output to the TMFFOUT. After having matched with the CPRAn, the counter
continues counting. When the value set to the CPRBn and the count value match, the timer flip-
flop shall be reversed to clear the counter. The CPRA must be smaller than the CPRB. The
initial status of the timer flip-flop can be set up in the flip-flop initialize (FFI) of the pulse
generator mode register (PGMRn; n=2,1).
When the count value matches the value of CPRA, a flag (“1”) is hoisted to the timer pulse
generator interrupt CPRA status (TPIAS) of the TISRn. The interrupt control logic asserts the
timer interrupt request TMINTREQ* when 1 is set to the timer pulse generator interrupt CPRA
enable (TPIAE) of the PGMRn. When 0 is set to the TPIAE, the TMINTREQ* shall not be
asserted. By writing in “0” into the TPIAS of the TISRn, the TPIAS shall be cleared and the
TMINTREQ* shall be deasserted. When the timer pulse generator interrupt CPRB enable
(TPIBE) is set to 1, a flag (“1”) shall be hoisted in the TPIBS of the TISRn when matching with
the CPRBn to assert TMINTREQ*. By writing in “0”, the TPIBS shall be cleared and the
TMINTREQ* shall be deasserted.
The counter clock can select the internal system clock and the external input clock. The
selection of the clock is conducted in the CCS of the TCRn. (Timer 0 can only be used with the
internal system clock.)
When using the internal system clock, it can be divided. The set up of the divider is conducted
by the CCD of the divider register when the CCDE of the TCRn is 1. From 2
1
to 2
8
dividing of
the internal system clock can be set up. Count operations are conducted at the rising of the
clock.
When using the external input clock, the edge of the clock can be selected in the ECES of the
TCRn.