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| 型号： | TMS320VC5409GGU100 |
| 厂商： | Texas Instruments |
| 文件页数： | 32/93页 |
| 文件大小： | 0K |
| 描述： | IC DIG SIG PROCESSOR 144-BGA |
| 标准包装： | 160 |
| 系列： | TMS320C54x |
| 类型： | 定点 |
| 接口： | 主机接口，McBSP |
| 时钟速率： | 100MHz |
| 非易失内存： | ROM（32 kB） |
| 芯片上RAM： | 64kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LFBGA |
| 供应商设备封装： | 144-BGA MICROSTAR（12x12） |
| 包装： | 托盘 |
| 配用： | 296-15829-ND - DSP STARTER KIT FOR TMS320C5416 |
| 其它名称： | 296-10763 296-10763-5 296-10763-5-ND |
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Functional Overview
38
April 1999 Revised October 2008
SPRS082F
3.3.5 DMA Controller
The 5409 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA controller allows movements of data to and from internal program/data
memory, internal peripherals (such as the McBSPs), and external program/data memory to occur in the
background of CPU operation. The DMA has six independent programmable channels allowing six different
contexts for DMA operation.
The DMA has the following features:
The DMA has external memory access.
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
post-decremented, or be adjusted by a programmable value.
Each internal read or write transfer may be initialized by selected sync events.
Each DMA channel is capable of sending interrupts to the CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only)
3.3.5.1
DMA External Access
The 5409 DMA supports external accesses to extended program, extended data, and extended I/O memory.
These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be used
for external memory accesses. The DMA external accesses require 9 cycle minimums for external writes and
13 cycle minimums for external reads.
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the
external bus the other will be heldoff via wait states until the current transfer is complete. The DMA takes
precedence over XIO requests. The HOLD/HOLDA feature of the 5409 affects external CPU transfers as well
as external DMA transfers. When an external processor asserts the HOLD pin to gain control of the memory
interface, the HOLDA signal is not asserted until all pending DMA transfers are complete. To prevent the DMA
from blocking out the CPU or HOLD/HOLDA feature from accessing the external bus, uninterrupted burst
transfers are not supported by the DMA. Subsequently, CPU and DMA arbitration testing is performed for
each external bus cycle, regardless of the bus activity.
Only two channels are available for external accesses. (One for external reads/one for external writes.)
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external to external transfers.
The DMA does not support synchronized external transfers.
The HM bit in the ST1 register indicates whether the processor continues internal execution when
acknowledging an active HOLD signal.
HM = 0, the processor continues execution from internal program memory but places its external interface
in the high impedance state.
HM = 1, the processor halts internal execution.
To ensure that proper arbitration occurs, the HM bit should be set to 0 in the memory-mapped ST1 register.
If the HM is set to 1 the processor will halt during DMA external transfers.
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