t-Time-25ms/div
50mA/div
10mA/div
I
PI
Inrush
V
VDD-VSS
Cvtr.Starts
V
RTN-VSS
Mark
Class
Detect
TPS23754
TPS23754-1
TPS23756
SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009
www.ti.com
PoE Startup Sequence
The waveforms of
Figure 23 demonstrate detection, classification, and startup from a PSE with type 2 hardware
classification. The key waveforms shown are VVDD-VVSS, VRTN-VVSS, and IPI. IEEE 802.3at requires a minimum of
two detection levels, two class and mark cycles, and startup from the second mark event. VRTN to VSS falls as the
TPS23754 charges CIN following application of full voltage. Subsequently, the converter starts up, drawing
current as seen in the IPI waveform.
Figure 23. Startup
Detection
The TPS23754 drives DEN to VSS whenever VVDD-VVSS is below the lower classification threshold. When the
input voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in
detection, RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 k (1%),
presents the correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A
valid PD detection signature is an incremental resistance (
ΔV / ΔI ) between 23.75 k and 26.25 k at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may be
hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is
partially cancelled by the TPS23754's effective resistance during detection.
The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage
into the detection range during the classification sequence. The PD is required to have an incorrect detection
signature in this condition, which is referred to as the mark event (see
Figure 23). After the first mark event, the
TPS23754 will present a signature less than 12 k
until it has experienced a VVDD-VVSS voltage below the mark
reset (VMSR). This is explained more fully under Hardware Classification.
Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with
power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to
determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in
hardware to indicate it is a high-power device. A type 1 PSE will treat a class 4 device like a class 0 device,
allotting 13 W if it chooses to power the PD. A PD that receives a 2 event class understands that it is powered
from a high-power PSE and it may draw up to 25.5 W immediately after the 80 ms startup period completes. A
type 2 PD that does not receive a 2-event hardware classification may choose to not start, or must start in a 13
W condition and request more power through the DLL after startup. The standard requires a type 2 PD to
indicate that it is underpowered if this occurs. Startup of a high-power PD under 13 W implicitly requires some
form of powering down sections of the application circuits.
18
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