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TPS23754
TPS23754-1
TPS23756
www.ti.com
SLVS885D – OCTOBER 2008 – REVISED DECEMBER 2009
The TPS23754 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some
situations or designers that prefer an R-C approach. The TPS23754 provides a pull-down on CS during the
GATE off time to improve sensing when an R-C filter must be used. The CS input signal should be protected
from nearby noisy signals like GATE drive and the switching MOSFET drain.
Dead Time
The TPS23754 features two switching MOSFET gate drivers to ease implementation of high-efficiency
topologies. Specifically, these include active (primary) clamp topologies and those with synchronous drivers that
are hard-driven by the control circuit. In all cases, there is a need to assure that both driven MOSFETs are not
on at the same time. The DT pin programs a fixed time period delay between the turn-off of one gate driver until
the turn-on of the next. This feature is an improvement over the repeatability and accuracy of discrete solutions
while eliminating a number of discrete parts on the board. Converter efficiency is easily tuned with this one
repeatable adjustment. The programmed dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE
transitions. The dead time is triggered from internal signals that are several stages back in the driver to eliminate
the effects of gate loading on the period, however the observed and actual dead-time will be somewhat
dependent on the gate loading. The turnoff of GAT2 coincides with the start of the internal clock period.
DT may be used to disable GAT2, which goes to a high-impedance state.
GATE’s phase turns the main switch on when it transitions high, and off when it transitions low. GAT2’s phase
turns the second switch off when it transitions high, and on when it transitions low. Both switches should be off
when GAT2 is high and GATE is low. The signal phasing is shown in
Figure 2. Many topologies that use
secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer.
The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding
FRS and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23754 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 78% and
controls the slope-compensation ramp circuit. Synchronization may be accomplished by applying a short pulse
(TSYNC) of magnitude VSYNC to FRS as shown in Figure 30. The synchronization pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.
T2P, Startup and Power Management
T2P (type 2 PSE) is an active-low multifunction pin that indicates if
[(PSE = Type_2) + (1.5 V < VAPD) + (1.55 V < VPPD< 8.3 V)] × (VCTL < 4 V) × (pd current limit ≠ Inrush).
The term with VCTL prevents an optocoupler connected to the secondary-side from loading VC before the
converter is started. The APD and PPD terms allow the PD to operate from an adapter at high-power if a type 2
PSE is not present, assuming the adapter has sufficient capacity. Applications must monitor the state of T2P to
detect power source transitions. Transitions could occur when a local power supply is added or dropped or when
a PSE is enabled on the far end. The PD may be required to adjust the load appropriately. The usage of T2P is
In order for a type 2 PD to operate at less than 13 W the first 80 ms after power application, the various delays
must be estimated and used by the application controller to meet the requirement. The bootup time of many
applications processors may be long enough to eliminate the need to do any timing.
Thermal Shutdown
The dc/dc controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver,
bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, and forces the
VC control into an under-voltage state.
Copyright 2008–2009, Texas Instruments Incorporated
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