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参数资料
型号： TPS65930BZCH
厂商： TEXAS INSTRUMENTS INC
元件分类： 消费家电
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA139
封装： 10 X 10 MM, 0.65 MM PITCH, GREEN, PLASTIC, NFBGA-139
文件页数： 4/115页
文件大小： 1232K
代理商： TPS65930BZCH
TPS65930/TPS65920
www.ti.com
SWCS037G
– MAY 2008 – REVISED APRIL 2011
The timing requirements listed in Table 12-7 are valid on the following conditions of input slew and output
load:
Rise and fall time range of inputs (SYNC, DIN) is tR/tF = 1.0 ns/6.5 ns
Capacitance load range of outputs (CLK, SYNC, DOUT) is CLoad = 1 pF/30 pF
Table 12-7. TDM Interface Master Mode
—Timing Requirements
Notation
Parameter
Min
Max
Unit
T3
tsu(DIN-CLKH)
Setup time, TDM.DIN valid to TDM.CLK
25
ns
high
T4
th(DIN-CLKH)
Hold time, TDM.DIN valid from TDM.CLK
0
ns
high
Table 12-8 lists the switching characteristics of the TDM interface master mode.
Table 12-8. TDM Interface Master Mode
—Switching Characteristics
Notation
Parameter
Min
Max
Unit
T0
tc(CLK)
Cycle time, TDM.CLK (1)
1/64 * Fs
ns
T1
tw(CLK)
Pulse duration, TDM.CLK high or low(2)
0.45*P
0.55*P
ns
Delay time, TDM.CLK rising edge to TDM.SYNC
–10
10
ns
T2
td(CLKL-SYNC)
transition
Delay time, TDM.CLK rising edge to TDM.DOUT
–10
12
ns
T5
td(CLKL-DOUT)
transition
(1)
Fs = 8 to 48 kHz; 96 kHz for RX path only
(2)
P = TDM.CLK period
12.5 JTAG Interfaces
The TPS65920/TPS65930 device JTAG TAP controller handles standard IEEE JTAG interfaces. This
section describes the timing requirements for the tools used to test TPS65920/TPS65930 device power
management.
The JTAG/TAP module provides a JTAG interface according to IEEE Std1149.1a. This interface uses the
four I/O pins TMS, TCK, TDI, and TDO. The TMS, TCK, and TDI inputs contain a pullup device, which
makes their state high when they are not driven. The output TDO is a 3-state output, which is high
impedance except when data are shifted between TDI and TDO.
TCK is the test clock signal.
TMS is the test mode select signal.
TDI is the scan path input.
TDO is the scan path output.
TMS and TDO are multiplexed at the top level with the GPIO0 and GPIO1 pins. The dedicated external
TEST pin switches from functional mode (GPIO0/GPIO1) to JTAG mode (TMS/TDO). The JTAG
operations are controlled by a state-machine that follows the IEEE Std1149.1a state diagram. This
state-machine is reset by the TPS65920/TPS65930 internal power-on reset (POR). A test mode is
selected by writing a 6-bit word (instruction) into the instruction register and then accessing the related
data register.
Table 12-9 and Table 12-10 assume testing over the recommended operating conditions (see
Figure 12-5).
Copyright
2008–2011, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
101
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