- 您现在的位置：买卖IC网 > PDF目录18733 > TRC101 (RFM)RFIC TRANCEIVER MULTI-CHANNEL FS PDF资料下载
参数资料
| 型号： | TRC101 |
| 厂商： | RFM |
| 文件页数： | 9/42页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANCEIVER MULTI-CHANNEL FS |
| 产品变化通告： | RFIC Obsolescence 15/Sept/2009 |
| 标准包装： | 1 |
| 系列： | TRC |
| 频率： | 300MHz ~ 1GHz |
| 数据传输率 - 最大： | 256kbps |
| 调制或协议： | FSK |
| 应用： | 通用 |
| 功率 - 输出： | 8dBm |
| 灵敏度： | -105dBm |
| 电源电压： | 2.2 V ~ 5.4 V |
| 电流 - 接收： | 17mA |
| 电流 - 传输： | 28mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 其它名称： | 583-1093-6 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
The FIFO can be read out through the SDO pin only by pulling the nFSEL pin (6) ‘Low” which selects the
FIFO for read and reading out data on the next SPI clock. The FINT pin (7) will stay active (logic ‘1’) until
the last bit has been read out, and it will then go ‘low’. This pin may also be polled to watch for valid data.
When the number of bits received in the FIFO match the pre-programmed limit, this pin will go active
(logic ‘1’) and stay active until the last bit is read out as above. An alternative method of reading the FIFO
is through an SPI bus Status Register read. The drawback to this is that all interrupt and status bits must
be read first before the FIFO bits appear on the bus. This could pose a problem for receiving large
amounts of data. The best method is using the SDO pin and the associated FIFO function pins.
Automatic Frequency Adjustment (AFA)
The PLL has the capability to do fine adjustment of the carrier frequency automatically. In this way, the
receiver can minimize the offset between transmit and receive frequency. This function may be enabled
or disabled through the Automatic Frequency Adjustment Register . The range of offset can be
programmed as well as the offset value calculated and added to the frequency control word within the
PLL to incrementally change the carrier frequency. The chip can be programmed to automatically
perform an adjustment or may be manually activated by a strobe signal. This function has the advantage
of allowing:
?
?
?
Low cost lower accuracy crystals to be used
Increased receiver sensitivity by narrowing the receive bandwidth
Achieving higher data rates
Crystal Oscillator
The TRC101 incorporates an internal crystal oscillator circuit that provides a 10MHz reference, as well as
internal load capacitors. This significantly reduces the component count required. The internal load
capacitance is programmable from 8.5pF to 16pF in 0.5pF steps. This has the advantage of accepting a
wide range of crystals from many different manufacturers having different load capacitance requirements.
Being able to vary the load capacitance also helps with fine tuning the final carrier frequency since the
crystal is the PLL reference for the carrier.
An external clock signal is also provided that may be used to run an external processor. This also has
the advantage of reducing component count by eliminating an additional crystal for the host processor.
The clock frequency is also programmable from eight pre-defined frequencies, each a pre-scaled value of
the 10MHz crystal reference. These values are programmable through the Battery Detect Threshold and
Clock Output Register . The internal clock oscillator may be disabled which also disables the output clock
signal to the host processor. When the oscillator is disabled, the chip provides an additional 196 clock
cycles before releasing the output, which may be used by the host processor to setup any functions
before going to sleep.
Frequency Control (PLL) and Frequency Synthesizer
The PLL synthesizer is the heart of the operating frequency. It is programmable and completely
integrated, providing all functions required to generate the carriers and tunability for each band. The PLL
requires only a single 10MHz crystal reference source. RF stability is controlled by choosing a crystal
with the particular specifications to satisfy the application. This gives the designer the maximum flexibility
in performance.
The PLL is able to perform manual and automatic calibration to compensate for changes in temperature
or operating voltage. When changing band frequencies, re-calibration must be performed. This can be
done by disabling the synthesizer and re-enabling again through the Power Management Register .
Registers common to the PLL are:
?
?
?
?
?
Power Management Register
Configuration Register
Frequency Setting Register
Automatic Frequency Adjust Register
Transmit Configuration Register
Data Quality Detector (DQD)
www.RFM.com
Email: info@rfm.com
Page 9 of 42
?by RF Monolithics, Inc.
TRC101 - 4/8/08
相关PDF资料 |
PDF描述 |
|---|---|
| MAX2051ETP+ | IC UP/DOWNCONVERSION MIXR 20TQFN |
| MAX9986ETP+ | IC MIXER DOWN CONV 20-TQFN |
| MAX9994ETP+ | IC MIXER DOWN CONV 20-TQFN |
| MAX9986AETP+ | IC MIXER DOWN CONV 20-TQFN |
| GLDC07B | SWTCH TOP PLNGR SNAP SPDT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TRC10-103 | 制造商:RCD 制造商全称:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-104 | 制造商:RCD 制造商全称:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-105 | 制造商:RCD 制造商全称:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-106 | 制造商:RCD 制造商全称:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
| TRC10-107 | 制造商:RCD 制造商全称:RCD COMPONENTS INC. 功能描述:RADIAL LEAD TANGOLDTM CAPACITORS EPOXY RESIN COATED, TANTALUM |
发布紧急采购，3分钟左右您将得到回复。