参数资料
型号: TSS463A-TERZ
厂商: Atmel Corp.
英文描述: VAN Data Link Controller with Serial Interface
中文描述: 凡数据与串行接口链路控制器
文件页数: 5/60页
文件大小: 816K
代理商: TSS463A-TERZ
5
TSS463-AA
4205B–AUTO–12/04
Microprocessor
Interface
The processor controls the TSS463AA by reading and writing the internal registers of
the circuit. These registers appear to the processor as regular memory locations.
Interface Modes
The TSS463AA must be connected with an SPI or SCI serial interface. The following
section provides information on switching from one mode to another.
Motorola SPI Mode
The first two bytes to be sent by the master (CPU) are called “Initialization Sequence”:
This sequence provides a proper asynchronous RESET in the TSS463AA and it selects
the Motorola SPI, Intel SPI or the SCI serial mode. This initialization sequence is shown
on Figure 4. Two 0x00 will cause an internal RESET and assert the Motorola SPI mode,
Two “0xFF” will provide an internal RESET and assert the Intel
SPI mode and “9 bits to
0 followed by 0xFF or 0xFE” will generate an internal RESET and assert the 9-bits SCI
mode.
Figure 2.
Mode Configuration Byte
The Motorola Serial Peripheral Interface (SPI) is fully compatible with the SPI Motorola
protocol. The interface is implemented for slave-mode only (the TSS463AA can not gen-
erate SPI frames by itself).
The SPI interface allows the interconnection of several CPUs and peripherals on the
same printed circuit board.
The SPI mode interface consists of 4 pins: separate wires are required for data and
clock, so the clock is not included in the data stream as shown in Figure 5. One pin is
needed for the serial clock (SCLK), two pins for data communication MOSI and MISO
and one pin for Slave Select (SS).
MOSI
or
MOSI
0 . 0000 . 0000
0x00
0xFF
SCLK
SS
SS
SCLK
SPI 8 Pulses
SCI 9 Pulses
0x00
0xFF
1 . 1111 . 1111
Internal RESET and SPI Mode (Intel or Motorola)
Internal RESET and SCI Mode
Intel
Motorola
Internal RESET
Internal RESET
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