参数资料
型号: UPD44646363AF5-E22-FQ1-A
厂商: Renesas Electronics America
文件页数: 3/42页
文件大小: 0K
描述: SRAM DDRII 72MBIT 165-PBGA
标准包装: 1
格式 - 存储器: RAM
存储器类型: SRAM - 同步,DDR II+
存储容量: 72M(2M x 36)
速度: 450MHz
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: 0°C ~ 70°C
封装/外壳: 165-LBGA
供应商设备封装: 165-PBGA(13x15)
包装: 散装

DATA SHEET
MOS INTEGRATED CIRCUIT
μ PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
72M-BIT DDR II+ SRAM
2.0 & 2.5 CLOCK CYCLES READ LATENCY
2-WORD BURST OPERATION
Description
The μ PD44646092A-A and μ PD44646093A-A are 8,388,608-word by 9-bit, the μ PD44646182A-A and μ PD44646183A-A
are 4,194,304-word by 18-bit and the μ PD44646362A-A and μ PD44646363A-A are 2,097,152-word by 36-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μ PD44646xx2A-A is for 2.0 clock cycles and the μ PD44646xx3A-A is for 2.5 clock cycles read latency. The
μ PD44646092A-A, μ PD44646093A-A, μ PD44646182A-A, μ PD44646183A-A, μ PD44646362A-A and μ PD44646363A-A
integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K
and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
? 1.8 ± 0.1 V power supply
? 165-pin PLASTIC BGA (15 x 17)
? HSTL interface
? DLL/PLL circuitry for wide output data valid window and future frequency scaling
? Pipelined double data rate operation
? Common data input/output bus
? Two-tick burst for low DDR transaction size
? Two input clocks (K and K#) for precise DDR timing at clock rising edges only
? Two Echo clocks (CQ and CQ#)
? Data Valid pin (QVLD) supported
? Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)
? Internally self-timed write control
? Clock-stop capability. Normal operation is restored in 20 μ s after clock is resumed.
? User programmable impedance output (35 to 70 Ω )
? Fast clock cycle time : 2.5 ns (400 MHz) for 2.0 clock cycles read latency,
2.0 ns (500 MHz) for 2.5 clock cycles read latency
? Simple control logic for easy depth expansion
? JTAG 1149.1 compatible test access port
? On-Die Termination (ODT) for better signal quality (Selectable ON/OFF by user)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M19960EJ2V0DS00 (2nd edition)
Date Published March 2010
Printed in Japan
2009, 2010
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